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dc.contributor.authorDadjou, Masoumeh
dc.date.accessioned2013-09-27 17:53:54 (GMT)
dc.date.available2013-09-27 17:53:54 (GMT)
dc.date.issued2013-09-27T17:53:54Z
dc.date.submitted2013
dc.identifier.urihttp://hdl.handle.net/10012/7964
dc.description.abstractIn modern cryptanalysis, an active attacker may induce errors during the computation of a cryptographic algorithm and exploit the faulty results to extract information about the secret key in embedded systems. This kind of attack is called a fault attack. There have been various attack mechanisms with diff erent fault models proposed in the literature. Among them, clock glitch faults support practically dangerous fault attacks on cryptosystems. This thesis presents an FPGA-based practical testbed for characterizing exploitable clock glitch faults and uniformly evaluating cryptographic systems against them. Concentrating on Advanced Encryption Standard (AES), simulation and experimental results illustrates proper features for the clock glitches generated by the implemented on-chip glitch generator. These glitches can be injected reliably with acceptably accurate timing. The produced faults are random but their eff ect domain is finely controllable by the attacker. These features makes clock glitch faults practically suitable for future possible complete fault attacks on AES. This research is important for investigating the viability and analysis of fault injections on various cryptographic functions in future embedded systems.en
dc.language.isoenen
dc.publisherUniversity of Waterlooen
dc.subjectfault attacken
dc.subjectclock glitchen
dc.subjectAESen
dc.subjectFPGAen
dc.titleAnalysis and Design of Clock-glitch Fault Injection within an FPGAen
dc.typeMaster Thesisen
dc.pendingfalseen
dc.subject.programElectrical and Computer Engineeringen
uws-etd.degree.departmentElectrical and Computer Engineeringen
uws-etd.degreeMaster of Applied Scienceen
uws.typeOfResourceTexten
uws.peerReviewStatusUnrevieweden
uws.scholarLevelGraduateen


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