Simplifying the Creation of Multi-core Processors: An Interconnection Architecture and Tool Framework
| dc.contributor.author | Grossman, Samuel Robert | |
| dc.date.accessioned | 2012-04-25T20:43:52Z | |
| dc.date.available | 2012-04-25T20:43:52Z | |
| dc.date.issued | 2012-04-25T20:43:52Z | |
| dc.date.submitted | 2012 | |
| dc.description.abstract | The contribution of this thesis is two-fold: an on-chip interconnection architecture designed specifically for multi-core processors and a tool framework that simplifies the process of designing a multi-core processor. Both contributions primarily target ASIC fabrication, though prototyping on an FPGA is also supported. SG-Multi, the on-chip interconnection architecture, distinguishes itself from other interconnection architectures by emphasizing universal adaptability; that is, a primary design goal is to ensure compatibility with industry-supplied cores originally intended for other architectures. This goal is achieved through the use of bus adapters and without introducing clock cycle latency. SG-Multi is a multi-bus architecture that uses slave-side arbitration and supports multiple simultaneous transactions between independent devices. All transactions are pipelined in two stages, an address phase and a data phase, and for improved performance slave devices must signal their status for a given clock cycle at the beginning of that cycle. SG-Multi Designer, the tool framework which builds systems that use SG-Multi, provides a higher level of abstraction compared to other competing system-building solutions; the set of components with which a designer must be concerned is much more limited, and low-level details such as hardware interface compatibility are removed from active consideration. Experimental results demonstrate that the hardware cost of using SG-Multi is reasonable compared to using a processor's native bus architecture, although the current implementation of arbitration is identifiable as an area for future improvement. It is also shown that SG-Multi is scalable; the reference systems grow linearly with respect to the number of cores when tested for ASIC fabrication and slightly sublinearly when tested for FPGA prototyping, and the maximum achievable clock frequency remains almost constant as the number of cores grows beyond four. Because the reference systems tested are an accurate reflection of the types of systems SG-Multi Designer produces, it is concluded that the abstraction model used by SG-Multi Designer does not over-simplify the design process in a way that causes excessive performance degradation or increased hardware resource consumption. | en |
| dc.identifier.uri | http://hdl.handle.net/10012/6648 | |
| dc.language.iso | en | en |
| dc.pending | false | en |
| dc.publisher | University of Waterloo | en |
| dc.subject | multi-core | en |
| dc.subject | EDA | en |
| dc.subject | hardware | en |
| dc.subject | Verilog | en |
| dc.subject | ASIC | en |
| dc.subject | FPGA | en |
| dc.subject.program | Electrical and Computer Engineering | en |
| dc.title | Simplifying the Creation of Multi-core Processors: An Interconnection Architecture and Tool Framework | en |
| dc.type | Master Thesis | en |
| uws-etd.degree | Master of Applied Science | en |
| uws-etd.degree.department | Electrical and Computer Engineering | en |
| uws.peerReviewStatus | Unreviewed | en |
| uws.scholarLevel | Graduate | en |
| uws.typeOfResource | Text | en |