Investigating Input Offset Reduction with Timing Manipulation in Low Voltage Sense Amplifiers
dc.contributor.author | Di Nardo, Matthew Joseph | |
dc.date.accessioned | 2021-02-18T14:39:24Z | |
dc.date.available | 2021-02-18T14:39:24Z | |
dc.date.issued | 2021-02-18 | |
dc.date.submitted | 2021-02-10 | |
dc.description.abstract | Static Random Access Memories (SRAMs) are ubiquitous in modern computer systems. They provide a fast and relatively compact method of data storage. SRAM cells are read from and written to using analog differential bitline signals, BL and BLB. To increase operating speed and conserve power during a read cycle, cell access time is limited to a short duration. Since SRAM are often implemented with near-minimum sized devices to maximize memory density, the devices are relatively weak and can only generate a limited differential voltage during this read window, typically between 10mV to 100mV. Standard logic devices cannot read this small signal, so sense amplifiers are used to rapidly amplify it to logic levels. A key metric for a sense amplifierโs performance is its input-referred offset voltage, ๐๐๐ . This dictates the minimum required input voltage to produce a correct decision. A lower ๐๐๐ means that a shorter read window for the SRAM is required, and the overall read cycle can be performed at a higher frequency. Unfortunately, with the trends of technology scaling, the effects of device mismatches from process variation are becoming more significant. In sense amplifiers, this device mismatch will create a statistical spread of ๐๐๐ with a mean and standard deviation of ๐๐๐ and ๐๐๐ . To guarantee error-free operation, a lower bound for input differential voltage is set by the worst-case scenario from this spread. Another difficulty introduced with modern trends is low voltage operation. The drive strengths of devices in lower VDD systems are weaker, so any imbalances due to threshold mismatch can become more significant compared to the nominal quantities. This thesis explores methods of reducing input offset voltage of low voltage SRAM sense amplifiers with a primary goal of reducing ๐๐๐ . A circuit called the Delayed PMOS VLSA, or DVLSA, is proposed. The DVLSA is based on the common VLSA and uses a timing manipulation technique with its control signals. The circuit design attempts to reduce ๐๐๐ by reducing the mismatch contribution of the PMOS pull-up pair. The circuit is tested at 0.4V with the VLSA used as a reference. Statistical simulations show that for the PMOS pull-up pair varying in isolation, the circuit works as intended and ๐๐๐ is reduced. When all differential devices are varied, the DVLSA has a larger ๐๐๐ . Investigating the source of the failure using the isolated variation of the other two device pairs shows that the timing manipulation technique has a negative impact on the NMOS pair. It also suggests that the use of the DLVSA architecture introduces additional covariances when all differential devices are varied. | en |
dc.identifier.uri | http://hdl.handle.net/10012/16811 | |
dc.language.iso | en | en |
dc.pending | false | |
dc.publisher | University of Waterloo | en |
dc.subject | sense amplifier | en |
dc.subject | cmos | en |
dc.subject | input offset voltage | en |
dc.title | Investigating Input Offset Reduction with Timing Manipulation in Low Voltage Sense Amplifiers | en |
dc.type | Master Thesis | en |
uws-etd.degree | Master of Applied Science | en |
uws-etd.degree.department | Electrical and Computer Engineering | en |
uws-etd.degree.discipline | Electrical and Computer Engineering | en |
uws-etd.degree.grantor | University of Waterloo | en |
uws-etd.embargo.terms | 0 | en |
uws.contributor.advisor | Sachdev, Manoj | |
uws.contributor.advisor | Wright, Derek | |
uws.contributor.affiliation1 | Faculty of Engineering | en |
uws.peerReviewStatus | Unreviewed | en |
uws.published.city | Waterloo | en |
uws.published.country | Canada | en |
uws.published.province | Ontario | en |
uws.scholarLevel | Graduate | en |
uws.typeOfResource | Text | en |