Investigating Input Offset Reduction with Timing Manipulation in Low Voltage Sense Amplifiers

Abstract

Static Random Access Memories (SRAMs) are ubiquitous in modern computer systems. They provide a fast and relatively compact method of data storage. SRAM cells are read from and written to using analog differential bitline signals, BL and BLB. To increase operating speed and conserve power during a read cycle, cell access time is limited to a short duration. Since SRAM are often implemented with near-minimum sized devices to maximize memory density, the devices are relatively weak and can only generate a limited differential voltage during this read window, typically between 10mV to 100mV. Standard logic devices cannot read this small signal, so sense amplifiers are used to rapidly amplify it to logic levels. A key metric for a sense amplifier’s performance is its input-referred offset voltage, 𝑉𝑜𝑠. This dictates the minimum required input voltage to produce a correct decision. A lower 𝑉𝑜𝑠 means that a shorter read window for the SRAM is required, and the overall read cycle can be performed at a higher frequency. Unfortunately, with the trends of technology scaling, the effects of device mismatches from process variation are becoming more significant. In sense amplifiers, this device mismatch will create a statistical spread of 𝑉𝑜𝑠 with a mean and standard deviation of 𝜇𝑜𝑠 and 𝜎𝑜𝑠. To guarantee error-free operation, a lower bound for input differential voltage is set by the worst-case scenario from this spread. Another difficulty introduced with modern trends is low voltage operation. The drive strengths of devices in lower VDD systems are weaker, so any imbalances due to threshold mismatch can become more significant compared to the nominal quantities. This thesis explores methods of reducing input offset voltage of low voltage SRAM sense amplifiers with a primary goal of reducing 𝜎𝑜𝑠. A circuit called the Delayed PMOS VLSA, or DVLSA, is proposed. The DVLSA is based on the common VLSA and uses a timing manipulation technique with its control signals. The circuit design attempts to reduce 𝜎𝑜𝑠 by reducing the mismatch contribution of the PMOS pull-up pair. The circuit is tested at 0.4V with the VLSA used as a reference. Statistical simulations show that for the PMOS pull-up pair varying in isolation, the circuit works as intended and 𝜎𝑜𝑠 is reduced. When all differential devices are varied, the DVLSA has a larger 𝜎𝑜𝑠. Investigating the source of the failure using the isolated variation of the other two device pairs shows that the timing manipulation technique has a negative impact on the NMOS pair. It also suggests that the use of the DLVSA architecture introduces additional covariances when all differential devices are varied.