APPENDIX to DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining
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Date
2020-03-02
Authors
Mirosanlou, Reza
Hassan, Mohamed
Pellizzoni, Rodolfo
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Abstract
Worst-case execution bounds for real-time programs are highly impacted by the latency of accessing hardware shared resources, such as off-chip DRAM. While many different memory controller designs have been proposed in the literature, there is a trade-off between average-case performance and predictable worst-case bounds, as techniques targeted at improving the former can harm the latter and vice-versa. We find that taking advantage of pipelining between different commands can improve both, but incorporating pipelining effects in worst-case analysis is challenging. In this work, we introduce a novel DRAM controller that successfully balances performance and predictability by employing a dynamic pipelining scheme. We show that the schedule of DRAM commands is akin to a two-stage two-mode pipeline, and hence, design an easily-implementable admission rule that allows us to dynamically add requests to the pipeline without hurting worst-case bounds.
Description
This document provides the appendix to: Reza Mirosanlou, Mohamed Hassan and Rodolfo Pellizzoni, DRAMbulism: Balancing Performance and Predictability through Dynamic Pipelining. Proceedings of the 26th IEEE Real-Time and Embedded Technology and Applications Symposium, Sydney, Australia, April 2020.
Keywords
Real-time systems, Memory Architecture, DRAM