Now showing items 21-31 of 31

    • Incorporating Physical Information into Clustering for FPGAs 

      Chen, Doris Tzu Lang (University of Waterloo, 2007-04-03)
      The traditional approach to FPGA clustering and CLB-level placement has been shown to yield significantly worse overall placement quality than approaches which allow BLEs to move during placement. In practice, however, ...
    • Mocarabe: High-Performance Time-Multiplexed Overlays for FPGAs 

      Mellat, Alireza (University of Waterloo, 2022-01-27)
      Coarse-grained reconfigurable array (CGRA) overlays can improve dataflow kernel throughput by an order of magnitude over Vivado HLS on Xilinx Alveo U280. This is possible with a combination of carefully floorplanned ...
    • A Multiprocessor Platform Based on FPGA Technology Targeted for a Driver Vigilance Monitoring Device 

      Moussa, Wafik (University of Waterloo, 2009-04-30)
      Medical devices processing images or audio or executing complex AI algorithms are able to run more efficiently and meet real time requirements if the parallelism in those algorithms is exploited. In this research a methodology ...
    • NengoFPGA: an FPGA Backend for the Nengo Neural Simulator 

      Morcos, Benjamin (University of Waterloo, 2019-08-22)
      Low-power, high-speed neural networks are critical for providing deployable embedded AI applications at the edge. We describe a Xilinx FPGA implementation of Neural Engineering Framework (NEF) networks with online learning ...
    • On the Use of Directed Moves for Placement in VLSI CAD 

      Vorwerk, Kristofer (University of Waterloo, 2009-07-31)
      Search-based placement methods have long been used for placing integrated circuits targeting the field programmable gate array (FPGA) and standard cell design styles. Such methods offer the potential for high-quality ...
    • Parallel Multiplier Designs for the Galois/Counter Mode of Operation 

      Patel, Pujan (University of Waterloo, 2008-06-09)
      The Galois/Counter Mode of Operation (GCM), recently standardized by NIST, simultaneously authenticates and encrypts data at speeds not previously possible for both software and hardware implementations. In GCM, data ...
    • Post-mapping Topology Rewriting for FPGA Area Minimization 

      Chen, Lei (University of Waterloo, 2009-08-26)
      Circuit designers require Computer-Aided Design (CAD) tools when compiling designs into Field Programmable Gate Arrays (FPGAs) in order to achieve high quality results due to the complexity of the compilation tasks involved. ...
    • Power Characterization of a Gbit/s FPGA Convolutional LDPC Decoder 

      Li, Si-Yun (University of Waterloo, 2012-08-31)
      In this thesis, we present an FPGA implementation of parallel-node low-density-parity-check convolutional-code (PN-LDPC-CC) encoder and decoder. A 2.4 Gbit/s rate-1/2 (3, 6) PN-LDPC-CC encoder and decoder were implemented ...
    • Side Channel Attack on Low Power FPGA Platform 

      Faraj, Mustafa (University of Waterloo, 2016-08-31)
      In today's advanced electronic age, people have become accustomed to using electronic devices to store and process their information. There is a general belief that the information is safe, due to the use of mathematically ...
    • Simplifying the Creation of Multi-core Processors: An Interconnection Architecture and Tool Framework 

      Grossman, Samuel Robert (University of Waterloo, 2012-04-25)
      The contribution of this thesis is two-fold: an on-chip interconnection architecture designed specifically for multi-core processors and a tool framework that simplifies the process of designing a multi-core processor. ...
    • Worst Case Latency Analysis for Hoplite FPGA-based NoC 

      Wasly, Saud; Pellizzoni, Rodolfo; Kapre, Nachiket (2017-10-30)
      Overlay NoCs, such as Hoplite, are cheap to implement on an FPGA but provide no bounds on worst-case routing latency of packets traversing the NoC due to deflection routing. In this paper, we show how to adapt Hoplite to ...


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