Real-Time FPGA-Based Testbed for Evaluating Digital Predistortion in Fully Digital MIMO Transmitters

Abstract

As one of the key enabling technologies of 5G networks, massive multiple-input, multiple-output (MIMO) transmitters use many transmit chains to ensure a very high data rate and acceptable signal quality. Realizing Massive MIMO not only includes increasing antenna count but also requires proportionally more power amplifiers (PAs). Digital predistortion (DPD) is a well-established signal processing method that mitigates the non-linearities of a PA when operated near saturation. Design tradeoffs must be carefully considered to reduce the system's overall power requirements given the high PA count in MIMO systems. This implies DPD power consumption for each transmission chain must be minimized. Apart from this, larger transmission bandwidths in next-generation networks require high hardware clock rates on the order of a few gigahertz. Current hardware can satisfy clock rates of up to hundreds of megahertz. Thus, there is a need for parallelized signal processing methods to meet bandwidth requirements.

This thesis investigates and addresses some challenges for deploying massive MIMO systems by designing and building a reconfigurable digital signal processing (DSP) testbed that allows for the implementation and validation of real-time DSP algorithms including DPD, for fully digital massive MIMO transceivers. This testbed allows transmission of up to 16 fully digital transmission chains at sub-6 GHz frequencies and supports up to 120 MHz of modulation bandwidths. Finally, a low-complexity and parallelized piecewise-linear (PWL) dual-input dual-output (DISO) DPD solution is proposed for linearizing MIMO transmitters. This DPD solution is realized with a commercially available field-programmable-gate-array (FPGA).