DuoMC: Tight DRAM Latency Bounds with Shared Banks and Near-COTS Performance
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Date
2021-09-27
Authors
Mirosanlou, Reza
Hassan, Mohamed
Pellizzoni, Rodolfo
Journal Title
Journal ISSN
Volume Title
Publisher
ACM International Symposium on Memory Systems (MEMSYS 2021)
Abstract
DRAM memory controllers (MCs) in COTS systems are designed primarily for average performance, offering no worst-case guarantees, while real-time MCs provide timing guarantees at the cost of a significant average performance degradation. For this reason, hardware vendors have been reluctant to integrate real-time solutions in high-performance platforms. In this paper, we overcome this performance-predictability trade-off by introducing DuoMC, a novel memory controller that promotes to augment COTS MCs with a real-time scheduler and run-time monitoring to provide predictability guarantees. Leveraging the fact that the resource is barely overloaded, DuoMC allows the system to enjoy the high performance of the conventional MC most of the time, while switching to the real-time scheduler only when timing guarantees risk being violated, which rarely occurs. In addition, unlike most existing real-time MCs, DuoMC enables the utilization of both private and shared DRAM banks among cores to facilitate communication among tasks. We evaluate DuoMC using a cycle-accurate multi-core simulator. Results show that DuoMC can provide better or comparable latency guarantees than state-of-the-art real-time MCs with limited performance loss (only 8% in the worst scenario) compared to the COTS MC.
Description
© {Reza Mirosanlou, Mohamed Hassan, and Rodolfo Pellizzoni | ACM} {2021}. This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in {In The International Symposium on Memory Systems }, https://doi.org/10.1145/3488423.3488431
Keywords
Memory Controller, DRAM, Predictability, Real-time Systems