dc.contributor.author | Mirosanlou, Reza | |
dc.contributor.author | Hassan, Mohamed | |
dc.contributor.author | Pellizzoni, Rodolfo | |
dc.date.accessioned | 2021-04-21 16:20:26 (GMT) | |
dc.date.available | 2021-04-21 16:20:26 (GMT) | |
dc.date.issued | 2021-02-05 | |
dc.identifier.uri | http://hdl.handle.net/10012/16893 | |
dc.description.abstract | The management of shared hardware resources in multi-core platforms has been characterized by a fundamental trade-off:
high-performance arbiters typically employed in COTS systems offer no worst-case guarantees,
while dedicated real-time controllers provide timing guarantees at the cost of significantly degrading system performance.
In this paper, we overcome this trade-off by introducing Duetto, a novel hardware resource management paradigm. Duetto pairs a real-time arbiter with a high-performance arbiter and a latency estimator module. Based on the observation that the resource is rarely overloaded, Duetto executes the high-performance arbiter most of the time, switching to the real-time arbiter only in the rare cases when the latency estimator deems that timing guarantees risk being violated. We demonstrate our approach on the case study of a multi-bank memory. Our evaluation based on cycle-accurate simulations shows that Duetto can provide the same latency guarantees as the real-time arbiter with limited loss of performance compared to the high-performance arbiter. | en |
dc.language.iso | en | en |
dc.publisher | IEEE Design, Automation and Test in Europe Conference (DATE) | en |
dc.subject | real-time systems | en |
dc.subject | memory architecture | en |
dc.subject | Duetto | en |
dc.title | Duetto: Latency Guarantees at Minimal Performance Cost | en |
dc.type | Conference Paper | en |
uws.contributor.affiliation1 | Faculty of Engineering | en |
uws.contributor.affiliation2 | Electrical and Computer Engineering | en |
uws.typeOfResource | Text | en |
uws.peerReviewStatus | Reviewed | en |
uws.scholarLevel | Graduate | en |