Millimetre Wave Series Connected Doherty PA Using 45nm SOI Process

Abstract

With the high demand for high data rate communication systems, it is expected that wireless networks will migrate into the unexploited millimeter-wave frequencies. This migration and the utilization of wide-band digitally modulated signal possessing of high Peak-to-Average-Power- Ratio (PAPR) brings diffcult challenges in attaining a satisfactory trade-off between linearity and efficiency when designing mm-wave power amplifiers (PAs). There are various methods of maximizing the output power and peak effciency of mm-wave PAs that use deep-sub-micron technologies. Of these methods, little attention has been given to the efficiency enhancement of PAs in back-off region. The use of the Doherty technique in the mm-wave frequencies has attracted little attention. This is mainly due to complexity in realizing the quarter-wave impedance inverter and the low-gain of the class-C operating peaking transistor using deep-sub-micron technologies. In this thesis, a series-connected-load (SCL) Doherty topology is proposed to enhance the efficiency of a millimeter-wave power amplifier realized on a deep-sub-micron semiconductor technology. The output combiner is determined by the ABCD matrices of the ideal combiner network in the SCL Doherty PA to ensure proper load modulation. Then, it describes the methodology applied to realize the transformer-based combiner networks while absorbing the parasitic capacitance of the transistors to maximize efficiency in the back-off region. This methodology is then applied to realize a two-stage SCL Doherty PA in 45 nm Silicon-on- Insulator CMOS technology to operate at 60 GHz.