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dc.contributor.authorSoliman, Muhammad Refaat Sedky
dc.contributor.authorPellizzoni, Rodolfo 18:29:40 (GMT) 18:29:40 (GMT)
dc.description.abstractIn recent years, the real-time community has produced a variety of approaches targeted at managing on- chip memory (scratchpads and caches) in a predictable way. However, to obtain safe Worst-Case Execution Time (WCET) bounds, such techniques generally assume that the processor is stalled while waiting to reload the content of on-chip memory; hence, they are less effective at hiding main memory latency compared to speculation-based techniques, such as hardware prefetching, that are largely used in general-purpose systems. In this work, we introduce a novel compiler-directed prefetching scheme for scratchpad memory that effectively hides the latency of main memory accesses by overlapping data transfers with the program execution. We implement and test an automated program compilation and optimization flow within the LLVM framework, and we show how to obtain improved WCET bounds through static analysis.en
dc.description.sponsorshipNSERC DG || 402369-2011 CMC Microsystemsen
dc.subjectGenetic algorithmen
dc.titleData Scratchpad Prefetching for Real-time Systemsen
dc.typeTechnical Reporten
dcterms.bibliographicCitationMuhammad R. Soliman and Rodolfo Pellizzoni: "Data Scratchpad Prefetching for Real-time Systems". Technical Report, University of Waterloo, May 2017en
uws.contributor.affiliation1Faculty of Engineeringen
uws.contributor.affiliation2Electrical and Computer Engineeringen

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