Electrical and Computer Engineering

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This is the collection for the University of Waterloo's Department of Electrical and Computer Engineering.

Research outputs are organized by type (eg. Master Thesis, Article, Conference Paper).

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0.42 THz Transmitter with Dielectric Resonator Array Antenna
(University of Waterloo, 2019-07-23) Holisaz, Hamed; Safavi-Naeini, Safieddin
Off chip antennas do not occupy the expensive die area, as there is no limitation on their building material, and can be built in any size and shape to match the system requirements, which are all in contrast to on-chip antenna solutions. However, integration of off-chip antennas with Monolithic-Microwave-Integrated Chips (MMIC) and designing a low loss signal transmission from the signal source inside the MMIC to the antenna module is a major challenge and trade off. High resistivity silicon (HRS), is a low cost and extremely low loss material at sub-THz. It has become a prevailing material in fabrication of passive components for THz applications. This work makes use of HRS to build an off-chip Dielectric Resonator Antenna Array Module (DRAAM) to realize a highly efficient transmitter at 420 GHz. This work proposes novel techniques and solutions for design and integration of DRRAM with MMIC as the signal source. A proposed scalable 4×4 antenna structure aligns DRRAM on top of MMIC within 2 μm accuracy through an effortless assembly procedure. DRAAM shows 15.8 dB broadside gain and 0.85 efficiency. DRAs in the DRAAM are differentially excited through aperture coupling. Differential excitation not only inherently provides a mechanism to deliver more power to the antenna, it also removes the additional loss of extra balluns when outputs are differential inside MMIC. In addition, this work proposes a technique to double the radiation power from each DRA. Same radiating mode at 0.42 THz inside every DRA is excited through two separate differential sources. This approach provides an almost loss-less power combining mechanism inside DRA. Two 140_GHz oscillators followed by triplers drive each DRA in the demonstrated 4×4 antenna array. Each oscillator generates 7.2 dBm output power at 140 GHz with -83 dBc/Hz phase noise at 100 KHz and consumes 25 mW of power. An oscillator is followed by a tripler that generates -8 dBm output power at 420 GHz. Oscillator and tripler circuits use a smart layer stack up arrangement for their passive elements where the top metal layer of the die is grounded to comply with the planned integration arrangement. This work shows a novel circuit topology for exciting the antenna element which creates the feed element part of the tuned load for the tripler circuit, therefore eliminates the loss of the transition component, and maximizes the output power delivered to the antenna. The final structure is composed of 32 injection locked oscillators and drives a 4×4 DRAAM achieves 22.8 dBm EIRP.
17-21 GHz Low-Noise Amplifier with Embedded Interference Rejection
(University of Waterloo, 2023-01-06) Jodhka, Tejasvi; Boumaiza, Slim; Nezhad-Ahmadi, Mohammad-Reza
The ever-growing demand for high performance wireless connectivity has led to the development of fifth-generation (5G) wireless communication standards as well as satellite communication (Satcom). Both 5G wireless communications and Satcom use higher carrier frequencies than traditional standards such as 4G and WiFi. While the higher carrier frequencies allow for larger bandwidths and faster data rates, they come with the cost of high free-space path loss. This high loss necessitates the use of active phased array antennas, which can require hundreds of integrated circuits (ICs) designed in Complimentary Metal-Oxide Semiconductor (CMOS) processes. Furthermore, in a future world with ubiquitous 5G wireless base stations and Satcom users, it is conceivable that Satcom receivers can be jammed by high-power Satcom transmitters and 5G signals. Therefore, Satcom phased arrays must be designed for resilience against these sources of interference while supporting high data rates. One of the key components in a Satcom receiver is the low-noise amplifier (LNA). It is responsible for amplifying the weak, noisy signal received from the satellite into a signal with sufficiently high signal-to-noise ratio for demodulation. One possible solution for making the phased array resilient to sources of interference is to embed filtering in the LNA. This thesis presents two LNA designs that employ embedded filtering for resiliency to interference from 5G wireless signals and Satcom transmitters. First, the circuit-level specifications of a 17.7 - 21.2 GHz (K-band) LNA for satellite communication phased array beamformers are derived from the system requirements. Next, the LNA designs are presented. The first LNA is designed to have out-of-band filtering at 24-30 GHz, which corresponds to the bands containing both 5G and Satcom transmitter interferers. The second LNA is designed to have out-of-band filtering at 27-30 GHz, which addresses a different scenario where the Satcom transmitter is the sole source of interference. Both LNAs are implemented in the Global Foundries 130nm 8XP Silicon-Germanium Bipolar CMOS (SiGe BiCMOS) process. A novel transformer feedback notch is introduced that enhances the filtering capabilities of the amplifier. The full electromagnetic simulation of the first LNA shows a peak gain of 28.8 dB, a minimum noise figure of 1.85 dB, and and input 1 dB compression point (IP1dB) greater than -17 dBm between 24 and 30 GHz. The second LNA shows a peak gain of 27.9 dB, a minimum noise figure of 1.78 dB, and an IP1dB greater than -15 dBm between 27 and 30 GHz. Both LNAs meet specifications sufficient for a Satcom receiver at the same time as having resiliency to out-of-band interference sources.
22-32 GHz Low-Noise Amplifier Design in 22-nm CMOS-SOI Technology
(University of Waterloo, 2019-01-29) Cui, Bolun; Long, John
This thesis explores the use of a 22-nm CMOS-SOI technology in the design of a two-stage amplifier which targets wide bandwidth, low noise and modest linearity in the 28 GHz band. A design methodology with a transformer-coupled, noise-matching interstage is presented for minimizing the noise factor of the two-stage amplifier. Furthermore, benefits of interstage noise matching are discussed. Next, a transistor layout for minimizing noise and maintaining sufficient electromigration reliability is described. It is followed by an analysis of transformer configurations and a transformer layout example is depicted. To verify the design methodology, two amplifier prototypes with noise-matching interstage were fabricated. Measurement shows that the first design achieves a peak gain of 20.7 dB and better-than-10-dB input and output return losses within a frequency range of 22.5 to 32.2 GHz. The lowest noise figure of 1.81 dB is achieved within the frequency range. Input IP3 of -13.4 dBm is achieved with the cost of 17.3 mW DC power consumption. When the bias at the back-gate is lowered from 2 V to 0.62 V, the power consumption is decreased to 5.6 mW and the peak gain drops down to 17.9 dB. Minimum noise figure increases from 1.81 to 2.13 dB and input IP3 drops to -14.4 dBm. The folded output stage in the second design improves the input IP3 to -6.7 dBm at the cost of 35 mW total power consumption. The peak gain of the second design is 20.1 dB, and the lowest noise figure of 1.73 dB within a frequency range of 23.8 to 32.4 GHz. Both designs occupy about 0.05 mm2 active area.
2D Digital Filter Implementation on a FPGA
(University of Waterloo, 2011-08-31T18:27:59Z) Tsuei, Danny Teng-Hsiang
The use of two dimensional (2D) digital filters for real-time 2D data processing has found important practical applications in many areas, such as aerial surveillance, satellite imaging and pattern recognition. In the case of military operations, real-time image pro-cessing is extensively used in target acquisition and tracking, automatic target recognition and identi cation, and guidance of autonomous robots. Furthermore, equal opportunities exist in civil industries such as vacuum cleaner path recognition and mapping and car collision detection and avoidance. Many of these applications require dedicated hardware for signal processing. It is not efficient to implement 2D digital filters using a single processor for real-time applications due to the large amount of data. A multiprocessor implementation can be used in order to reduce processing time. Previous work explored several realizations of 2D denominator separable digital filters with minimal throughput delay by utilizing parallel processors. It was shown that regardless of the order of the filter, a throughput delay of one adder and one multiplier can be achieved. The proposed realizations have high regularity due to the nature of the processors. In this thesis, all four realizations are implemented in a Field Programming Gate Array (FPGA) with floating point adders, multipliers and shift registers. The implementation details and design trade-offs are discussed. Simulation results in terms of performance, area and power are compared. From the experimental results, realization four is the ideal candidate for implementation on an Application Specific Integrated Circuit (ASIC) since it has the best performance, dissipates the lowest power, and uses the least amount of logic when compared to other realizations of the same filter size. For a filter size of 5 by 5, realization four can produce a throughput of 16.3 million pixels per second, which is comparable to realization one and about 34% increase in performance compared to realization one and two. For the given filter size, realization four dissipates the same amount of dynamic power as realization one, and roughly 54% less than realization three and 140% less than realization two. Furthermore, area reduction can be applied by converting floating point algorithms to fixed point algorithms. Alternatively, the denormalization and normalization stage of the floating point pipeline can be eliminated and fused together in order to save hardware resources.
A 37-40 GHz Dual-Polarized 16-Element Phased-Array Antenna with Near-Field Probes
(University of Waterloo, 2022-09-21) He, Ziran; Boumaiza, Slim
With the development of fifth-generation (5G) communication networks, in order to meet the growing demand for high-speed and low-latency wireless communication services, channel capacity has become the main driving force for choosing millimeter wave (mm-wave) over over-crowded sub-6 GHz frequency bands. Recently, beamforming phased array attracts significant research efforts as it is a promising solution and unique in its ability to overcome the high path-loss at high frequency, provide fast beam steering and deliver better user-ends experience. However, to alleviate the issues that associated with beamforming phased array, such as imbalance between array elements and non-linearity caused by power-amplifiers (PAs) in beamforming channels, far-field (FF) based array calibration and digital pre-distortion (DPD) need to be performed, which is not practical in real world scenario. This thesis presents a low-cost 16-element dual-polarized mm-wave antenna-on-printed circuit board (PCB) transmitter RF beamforming array with embedded near-field probes (NFPs) at 37-40 GHz. The elements are orthogonal, proximity-coupled feed dual-polarized patch antenna with a spacing of 0.5λ within 2x2 subarray and 0.6λ between 2x2 subarray at 38.5 GHz, resulting in maximum 17.7 dB gain with a scan angle of +/-50◦, +/-20◦ in azimuth and +/-20◦, +/-50◦ in elevation for vertical polarization and horizontal polarization, respectively. Without affecting phased array performance, the NFPs achieve flat and comparable coupling magnitude and group delay to the closet RF chain for both polarizations, across operating frequency range. This ensures the quality of received output signal from phased array to implement array calibration and DPD. The configuration of embedded NFPs maintains the scalability of phased array and eliminate the needs of impractical FF reference probe for array calibration and DPD.
A 39GHz Balanced Power Amplifier with Enhanced Linearity in 45 nm SOI CMOS
(University of Waterloo, 2022-09-20) Ma, Haien; Boumaiza, Slim
With the high data rate communication systems that come with fifth-generation (5G) mobile networks, the shift of operation to millimeter-wave frequency becomes inevitable. The expected data rate in 5G is significantly improved over 4G by utilizing the large available channel bandwidth at millimeter wave frequencies and complex data modulation schemes. With this increase in operation frequency, many new challenges arise and research efforts are made to tackle them. Among them, the phased array system is one of the hottest topics as it can be made use of to improve the link budget and overcome the path loss challenge at these frequencies. As the last circuit component in the transmitter's front-end right before the antenna, the power amplifier (PA) is one of the most crucial components with significant effects on overall system performance. Many of the traditional challenges of CMOS PA design such as output power and efficiency, are now compounded with the additional challenges that are imposed on complementary metal-oxide semiconductor (CMOS) PAs in millimeter wave phased array systems. This thesis presents a balanced power amplifier design with enhanced linearity in GlobalFoundries' 45nm silicon-on-insulator (SOI) CMOS technology. By using the balanced topology with each stage terminating with a differential 2-stacked architecture, the PA achieves saturated output power of over 21 dBm. Each of the two identical sub-PAs in the balanced topology uses 2-stage topology with driver and PA co-design method. The linearity is enhanced through careful choice of biasing point and a strategic inter-stage matching network design methodology, resulting in amplitude-to-phase distortion below 1 degree up to the output 1dB compression level of over 19 dBm. The balanced amplifier topology significantly reduces the PA performance variation over mismatched load impedance at the output, thus improving the PA performance over different antenna active impedance caused by varying phased array beam-steering angles. In addition to this, the balanced topology also optimizes the PA input and output return loss, giving a better matching than -20 dB at both input and output, and minimizing the risk of potential issues and performance degradation in the system integration phase. Lastly, the compact transformer based matching networks and quadrature hybrids reduce the chip area occupation of this PA, resulting in a compact design with competitive performance.
45-nm SOI CMOS Bluetooth Electrochemical Sensor for Continuous Glucose Monitoring
(University of Waterloo, 2018-08-21) Muthreja, Aman; Long, John; Levine, Peter
Due to increasing rates of diabetes, non-invasive glucose monitoring systems will become critical to improving health outcomes for an increasing patient population. Bluetooth integration for such a system has been previously unattainable due to the prohibitive energy consumption. However, enabling Bluetooth allows for widespread adoption due to the ubiquity of Bluetooth-enabled mobile devices. The objective of this thesis is to demonstrate the feasibility of a Bluetooth-based energy-harvesting glucose sensor for contact-lens integration using 45~nm silicon-on-insulator (SOI) complementary metal-oxide-semiconductor (CMOS) technology. The proposed glucose monitoring system includes a Bluetooth transmitter implemented as a two-point closed loop PLL modulator, a sensor potentiostat, and a 1st-order incremental delta-sigma analog-to-digital converter (IADC). This work details the complete system design including derivation of top-level specifications such as glucose sensing range, Bluetooth protocol timing, energy consumption, and circuit specifications such as carrier frequency range, output power, phase-noise performance, stability, resolution, signal-to-noise ratio, and power consumption. Three test chips were designed to prototype the system, and two of these were experimentally verified. Chip 1 includes a partial implementation of a phase-locked-loop (PLL) which includes a voltage-controlled-oscillator (VCO), frequency divider, and phase-frequency detector (PFD). Chip 2 includes the design of the sensor potentiostat and IADC. Finally, Chip 3 combines the circuitry of Chip 1 and Chip 2, along with a charge-pump, loop-filter and power amplifier to complete the system. Chip 1 DC power consumption was measured to be 204.8~$\mu$W, while oscillating at 2.441 GHz with an output power $P_{out}$ of -35.8 dBm, phase noise at 1 MHz offset $L(1\text{ MHz})$ of -108.5 dBc/Hz, and an oscillator figure of merit (FOM) of 183.44dB. Chip 2 achieves a total DC power consumption of 5.75~$\mu$W. The system has a dynamic range of 0.15~nA -- 100~nA at 10-bit resolution. The integral non-linearity (INL) and differential non-linearity (DNL) of the IADC were measured to be -6~LSB/$\pm$0.3~LSB respectively with a conversion time of 65.56~ms. This work achieves the best duty-cycled DC power consumption compared to similar glucose monitoring systems, while providing sufficient performance and range using Bluetooth.
5G Fixed Wireless Access for Bridging the Rural Digital Divide
(University of Waterloo, 2021-09-22) Lappalainen, Andrew; Rosenberg, Catherine
Despite the ubiquitous level of mobile and fixed broadband (FB) connectivity that exists for many people today, the availability of high quality FB services in rural communities is generally much lower than in urban communities, which has led to a digital divide. At the same time, rural communities in Canada have a high level of 4G LTE coverage and the mobile digital divide between urban and rural communities is much smaller compared to the FB divide. Traditionally, FB and mobile services were offered over separate technologies by different operators, and evolved separately from one another. However, recently, a convergence between mobile and FB has started to emerge via 4G Fixed Wireless Access (FWA), which has made it possible to take advantage of the high level of cellular coverage in rural communities to offer (limited) FB at lower costs than traditional wired FB. To bridge the digital divide, rural FWA must be able to provide the same end-to-end experience as urban FB. In in this regard, 4G FWA has been inadequate; however, the recent emergence of 5G, which brings new spectrum, a more efficient radio interface, and multi-user massive MIMO, can make a difference. In the first half of this thesis we outline a vision for how 5G could fix the rural connectivity gap by truly enabling FWA in rural regions. We examine new and upcoming improvements to each area of the 5G network architecture and how they can benefit rural users. Despite those advancements, 5G operators will face a number of challenges in planning and operating rural FWA networks. Therefore, we also draw attention to a number of open research challenges that will need to be addressed. In the latter half of this thesis, we study the planning of a rural 5G multi-user massive MIMO FWA TDD system to offer fixed broadband service to homes. Specifically, we aim to determine the user limit, i.e., the maximum number of homes that can simultaneously receive a target minimum bit rate (MBR) on the downlink (DL) and a target MBR on the uplink (UL) given a set of network resources (e.g., bandwidth, power, antennas) and given a radius. To attain that limit, we must understand how resources should be shared between the DL and UL and how user selection (as well as stream selection since both the base-station (BS) and the homes are multi-antenna), precoding and combining, and power distribution should be performed. To simplify the problem, we use block diagonalization and propose a static user grouping strategy that organizes homes into fixed groups in the DL and UL (we use different groups for the two directions); then we develop a simple process to find the user limit by determining the amount of resources required to give groups the MBRs. We study the impact of group sizes and show that smaller groups use more streams and enable more homes to receive the MBRs when using a 3.5~GHz band. We then show how the user limit at different cell radii is impacted by the system bandwidth, the number of antennas at the BS and homes, the BS power, and the DL and UL MBRs. Lastly, we offer insight into how the network could be operated for an arbitrary number of homes.
60 Watts Broadband Push Pull RF Power Amplifier Using LTCC Technology
(University of Waterloo, 2013-09-27T15:39:59Z) Jundi, Ayman
The continuous increase in wireless usage forces an immense pressure on wireless communication in terms of increased demand and spectrum scarcity. Service providers for communication services had no choice but to allocate new parts of the spectrum and present new communication standards that are more spectrally efficient. Communication is not only limited to mobile phones but recently attention has been given to intelligent transportation systems (ITS) where cars will be given a significant place in the communication network. Vehicular Ad-Hoc Network (VANET) is already assigned a slice of the spectrum at 5.9GHz using the IEEE802.11p standard also known as Dedicated Short-Range Communication (DSRC); however, this assignment will have limited range and functionality at first, and users are expected to depend on existing wireless mobile channels for some services such as video streaming and car entertainment. Therefore, it is essential to integrate existing wireless mobile communication standards into the skeleton of ITS at launch and most probably permanently. An investigation was carried out regarding the existing communication standards including wireless local area networks (WLAN) and it was found that frequency bands from 400MHz up to 6GHz are being used in various regions around the world. It is also noted that current state of the art transceivers are composed of several transmitter front-ends targeting certain bands and standards. However, the more standards to be supported the more components to be added and the higher the cost not to mention the limited space in mobile devices. Multimode Multiband (MMMB) transmitters are therefore proposed as a potential solution to the existing redundancy in the number of front-end paths in modern transmitters. Broadband amplifiers are an essential part of any MMMB transmitter and they are also among the most challenging especially for high power requirements. This work explains why single ended topologies with efficiencies higher than 50% have a fundamental bandwidth limit such that the highest frequency of operation must be lower than twice the lowest frequency of operation. Hence, Push-Pull amplifier topology is being proposed as it was found that it has inherent broadband capabilities exceeding those of other topologies with comparable efficiency. The major advantage of Push-Pull power amplifiers is its capability of isolating the even harmonics present in the even mode operation of a Push-Pull amplifier from the less critical odd mode harmonics and the fundamental frequency. This separation between even and odd signals comes from the inclusion of a Balun at the output of push-pull amplifiers. Such separation makes it possible to operate amplifiers beyond the existing limit of single ended power amplifiers. To prove the concept, several Baluns were designed and tested and a comparison was made between different topologies in terms of balance, bandwidth and odd and even mode performances; moreover, to illustrate the concept a Push-Pull power amplifier design was implemented using the multilayer Low Temperature Co-fired Ceramics (LTCC) technology with a bandwidth ratio of more than 100%.
A Comprehensive Framework Incorporating Hybrid Deep Learning Model, Vi-Net, for Wildfire Spread Prediction and Optimized Safe Path Planning
(University of Waterloo, 2025-02-11) Dhindsa, Manavjit Singh; Naik, Kshirasagar
Forest fires are becoming more prevalent than ever, and their intensity and frequency are expected only to increase owing to climate change and environmental degradation. These fires severely threaten the economy, human lives, and infrastructure. Therefore, effective management of wildfires is of utmost importance, and accurately predicting the wildfire spread lies at the core of it. Reliable predictions of fire spread not only provide insights about the at-risk regions but also help in planning several mitigation activities including resource allocation and evacuation planning. This thesis introduces Vi-Net, an innovative hybrid deep learning model, which integrates the localized precision of U-Net with the global contextual awareness of Vision Transformers (ViT) to predict next-day wildfire spread with unprecedented accuracy. This study utilizes an extensive multimodal dataset that accumulates data from different sources across the United States from 2012 to 2020 incorporating critical factors such as topographical, meteorological, anthropological (population density), and vegetation indices. These elements are vital for modeling the complex dynamics of wildfire spread. A significant challenge in this domain is the class imbalance as the fire points are generally quite less compared to non-fire points. The dataset used in this study had fire regions less than 5% of the total data. To address this issue, advanced loss functions, including Focal Tversky Loss (FTL), are employed, prioritizing accurate segmentation of fire-prone regions while minimizing false negatives. FTL modifies the focus towards hard-to-predict regions and crucial boundaries, thereby enhancing the model's predictive accuracy and reliability in practical scenarios. Vi-Net addresses the complexities in modeling fire dynamics by synergizing the strengths of U-Net and ViT. Integrating U-Net and ViT in Vi-Net allows for a comprehensive analysis that ensures high precision and recall, effectively balancing the sensitivity and specificity needed in wildfire predictions. This dual approach allows the model to process detailed local information and extensive contextual data, making it exceptionally capable of identifying and predicting fire spread across diverse landscapes. Experimental results highlight the superiority of Vi-Net over traditional models, achieving an F1 Score of 97.25% and an Intersection over Union (IoU) of 94.15% on the test dataset. These metrics highlight its capability to accurately capture localized fire patches and long-range dependencies while avoiding overprediction. These advancements validate the model's potential to offer more nuanced predictions, capturing the interplay between micro and macro-level environmental dynamics. In addition to predictive modeling, this research extends its practical applicability by integrating the predicted fire masks into an optimized A* algorithm for safe path planning. This step ensures actionable insights for emergency response teams, facilitating efficient evacuation routes and resource allocation while avoiding high-risk fire regions. Qualitative and quantitative analyses confirm the hybrid model's efficacy, with visualizations demonstrating Vi-Net’s ability to preserve spatial detail while capturing broad environmental contexts, and path planning results illustrating the model's robustness and reliability. This research not only sets a new benchmark for wildfire prediction models but also demonstrates the potential of hybrid deep learning systems in environmental science applications. By providing a robust framework for real-time wildfire management, Vi-Net could significantly influence future strategies in disaster response and resource allocation. Future enhancements could include integrating real-time data feeds to further improve the adaptability and predictive capabilities of the model, potentially revolutionizing wildfire management practices globally.
A Comprehensive Process for Addressing Market Power in Decentralized ADN Electricity Markets
(University of Waterloo, 2025-03-05) AboAhmed, Yara; Salama, Magdy; Bhattacharya, Kankar
Electric power systems have transformed globally, with distribution grids evolving into active distribution networks (ADNs), altering their characteristics and operations. Traditional centralized market structures have become inadequate for the complexities of the ADNs, leading to inefficiencies and challenges in reliable operation and energy pricing. ADN electricity markets offer a solution by leveraging smart grid features to integrate distributed energy resources (DERs), allowing non-utility entities, such as producers, consumers and prosumers, to participate directly, enhancing market efficiency, reducing monopoly power, and limiting utility control over prices. However, with the increasing penetration of DERs, there is a growing risk of market concentration and manipulation by entities owning large shares of DERs in ADN electricity markets. This poses a potential threat to market fairness, as some participants may exploit market power, leading to an uneven playing field, reducing the integrity and efficiency of ADN electricity markets. From this standpoint, this thesis investigates and adapts the concept of market power within ADN electricity markets, considering the unique characteristics of the market and the system. The investigation is structured around six central questions: (1) Can non-utility entities exercise market power in ADN electricity markets? (2) Is there a comprehensive framework for accurately monitoring, evaluating, and mitigating market power in decentralized ADN markets? (3) If such a framework exists, can it manage the complexity of monitoring the large number of ADN market participants? (4) If market power manipulation exists, are current investigations adequate, considering the decentralized market structure, the physical characteristics of the system, DER operational constraints, and the interplay between active and reactive power markets? (5) What types of decentralized market structures and frameworks—such as fully decentralized, community-based, or network-based peer-to-peer (P2P)—are appropriate for addressing market power in ADN electricity markets? (6) Are traditional market power mitigation methods applicable and effective in the context of ADN electricity markets considering the decentralized nature of the ADN and the dispersed DERs?. The primary objective of this thesis is to develop a fair and decentralized energy trading platform that limits monopoly power and mitigates market power abuse in ADN electricity markets. To achieve this goal, the thesis proposes an innovative comprehensive process for monitoring, evaluating, and mitigating market power, specially designed for the decentralized structure of ADNs and their market frameworks. This process considers the shifts in network configuration as well as the physical and operational characteristics of ADNs and their components. The process begins by monitoring market power of dominant market participants through introducing the zoning concept. These operational zones narrow down the number of market participants within each zone, addressing the challenge of monitoring a large number of market participants with widely distributed DERs and improving the identification and control of potential market power exercisers, thus minimizing their potential market power. These operational zones serve as decentralized interfaces between the zonal market participants and their corresponding zonal market operators, establishing a decentralized platform for energy trading. The second stage of the process focuses on evaluating market power through investigating and analyzing the strategic offering behavior of the potential market power exercisers identified in stage one. This analysis is conducted within the framework of a community-based P2P decentralized ADN electricity market, considering the physical and operational characteristics of both the system and DERs, along with the coupled active and reactive power markets. A comparative evaluation of market outcomes under competitive and strategic conditions is performed to identify strategic manipulators. In this context, the study also examines the applicability and effectiveness of conventional market power mitigation techniques used for the centralized market and assesses their impact on the strategic offering behavior of identified manipulators. While some traditional market power mitigation techniques may demonstrate efficiency, a new approach is necessary to address the unique decentralization characteristic of ADN electricity markets. A novel market power mitigation technique is proposed in the third stage of the process, targeting the root cause of market power: market concentration. This approach introduces an innovative market zoning concept, dynamically partitioning the system into "Market-Zones" to reduce market concentration while adapting to different system operational conditions, considering the uncertainties in system demand and generation, thereby aligning with the decentralized nature of ADNs and their markets. The proposed innovative zoning approach offers a robust solution for mitigating market power in decentralized ADN electricity markets. Within these Market-Zones, each player can actively engage and participate in the market and obtain the benefit without being overtaken by entities with large market shares. Consequently, the market power of the dominant players is subsided and diluted by utilizing the proposed Market-Zones, establishing a fair energy trading platform.
A Compressive-Sensing-Capable CMOS Electrochemical Capacitance Image Sensor with Two-Dimensional Code-Division-Multiplexed Readout
(University of Waterloo, 2025-03-04) McLachlan, Shane; Levine, Peter
Electrochemical capacitance imaging is a technique used to observe biological analyte or processes at the surface of an electrode, immersed in an electrolyte, via small changes in capacitance. This technique has various applications in biosensing such as biomedical diagnostics, neural interfaces and DNA sensors. Complimentary metal-oxide-semiconductor (CMOS) technology is well suited for implementing electrochemical capacitance image sen- sors since high spatial resolution electrode arrays and readout circuitry can be integrated on the same chip. This thesis presents the design and simulation of a 256 × 256 pixel electrochemical capacitance image sensor fabricated in a 180-nm analog/mixed-signal CMOS process. Our image sensor features a novel two-dimensional code-division-multiplexed (2D CDM) readout architecture that directly outputs analog coefficients of the 2D Walsh transform of the image. To the best of our knowledge, we are the first to implement true 2D CDM readout in the capacitive image sensor space. For passive-pixel sensors, CDM readout yields a signal-to-noise ratio (SNR) increase over traditional time-division-multiplexed (TDM) readout through integrating orthogonal combinations of all pixels for the entire frame time. Use of the 2D Walsh transform enables compressive sensing at the time of array readout, which is achieved by exploiting the energy compaction property of the Walsh domain. Compressive sensing provides analog lossy image compression that can enable a frame rate increase or power consumption decrease. In addition, our transform domain readout architecture removes the layout requirement for pitch-matched column amplifiers, requiring only one larger column circuit for the full array. Some potential advantages introduced by this include reductions to both amplifier flicker noise and fixed-pattern noise from transistor mismatch. Our sensor uses two-transistor switched-capacitor pixels with a 3.2 × 3.2 μm² work- ing electrode and 3.88 μm grid pitch to enable charge-based capacitance measurement. On-chip 256-bit parallel Walsh code generators enable power efficient orthogonal code generation. Full-chip post-layout analog simulation with a biological capacitance image demonstrates that we can achieve a structural similarity index (SSIM) of 0.875 versus a reference image. SSIM values range from 0 to 1, where 1 indicates complete image similarity.
A Graph Neural Network Based Approach for Predicting Wildfire Burned Areas
(University of Waterloo, 2025-02-10) Das, Ursula; Naik, Kshirasagar
Wildfires annually cause substantial economic and environmental losses and has a detrimental impact on human lives and health due to the release of their harmful byproducts. Moreover, wildfire incidents have exhibited an alarming surge in frequency as well as severity in recent years due to increased urbanization near forested areas coupled with climate change, highlighting the need for advanced technologies to predict wildfire behavior in advance and mitigate its impact. In recent years, the enormous strides in machine learning research coupled with the increased availability of wildfire data through various sources such as remote sensing and the increased availability of computational resources have fueled the rise of data-driven approaches across all stages of wildfire management. Despite the growing adoption of machine learning-driven approaches in wildfire mitigation, the primary focus has been on analyzing historical patterns and identifying the causes leading to wildfire patterns rather than predicting wildfire behavior. The prediction of wildfire behavior over time, such as the burned area has been largely underexplored. This study aims to address this gap by advancing data-driven methods for predicting wildfire behavior during the active fire stage and aiding in resource allocation efforts. This study adopts a Graph Neural Network based framework for predicting the burned area resulting from a wildfire ignition. While CNN-based architectures have been widely employed to model wildfire behavior, including spread prediction, as a semantic segmentation task, these architectures impose specific limitations on geospatial data due to their reliance on fixed-size inputs and local receptive fields. Graph Neural Network (GNNs), have shown success in capturing the long-range dependencies and irregular-sized inputs inherent in geospatial data, such as wildfires, making them a viable alternative to CNNs. To this end, a GNN-based approach is adopted to model wildfire burned area prediction. A framework is developed to represent spatial wildfire data and its influencing factors as homogeneous graphs followed by the development of three distinct GNN models based on different message-passing mechanisms to process the graph-structured data. The results obtained through various experiments illustrate the efficacy of Graph Neural Networks in modeling wildfire behavior. In terms of Precision, most GNN models outperform the segmentation models, with the highest achieving a score of 0.4536. For AUROC, all GNN models demonstrate superior performance, reaching a maximum of 0.9377. Based on AUPRC, the Graph Convolutional Network (GCN) model surpasses all others, including segmentation models, with a top score of 0.4787. These findings underscore the potential of Graph Neural Networks (GNNs) as a powerful tool for wildfire behavior modeling and supporting resource allocation initiatives.
A Low-Cost Technique for improving Angular Scan Range of Phased Array Antennas
(University of Waterloo, 2025-01-22) Mostafa, Mahmoud; Abdel-Wahab, Wael; Majedi, Hamed
With the emergence of modern communication technologies, there has been an increasing demand for faster and higher-quality communication, which necessitates higher bit rates and, consequently, greater bandwidth. This shift has driven the adoption of higher operational frequencies, such as millimeter-wave bands. For instance, 5G mobile communications operate in the K band (18–27 GHz) and Ka band (27–40 GHz), while satellite communications often use the Ku band (12–18 GHz) and Ka band. However, as the operational frequency increases, path loss becomes significantly higher, requiring the use of higher-gain antennas to compensate for this loss. A key drawback of using high-gain antennas, such as parabolic reflectors, is the difficulty in steering the beam to cover a wider angular range. Phased array antennas provide an excellent solution as transmitting or receiving antennas for that reason, as they provide a high gain with the ability to electronically steer the beam to other directions by changing the progressive phase shift between the array elements. Designing a high-performance broadband phased array antenna with a wide angular scanning range is challenging, as the antenna parameters are interrelated and require tradeoffs. For example, increasing the distance between elements reduces mutual coupling and increases the effective aperture of the array, thereby enhancing its gain. However, this also causes grating lobes to appear at lower scan angles, thereby limiting the angular scanning range. Additionally, a larger element spacing necessitates a wider electronic phase shift range, requiring a more linear phase shifter with frequency, which complicates the design of the feeding network. The focus of this research is to investigate a low-cost approach to improving the angular scanning range of phased array antennas through the use of a wide angle impedance matching layer (WAIM), employing two techniques. First, A general analytical method is provided to characterize the array’s scan impedance variation in the presence of nearby reflecting surfaces, such as a ground plane or WAIM layers. Second, the generalized Smatrix technique is used to model the array unit cell and transmission line (TL) models for WAIM layers. The WAIM layer offers a low-cost, scalable solution to increase the angular scanning range of phased array antennas without altering their lattice configuration or feeding network. This makes it a modular solution, simpler than other techniques. In this thesis, Both main WAIM modeling techniques are investigated, applied to different array examples (slot and dipole arrays). Then, the GSM method is used to design a fully dielectric WAIM layer
A Novel PLC Front-haul for 5G IoT Indoor Communication using Split C-RAN Architecture
(University of Waterloo, 2024-08-23) Ibrahim, Mai; Ho, Pin-Han
The demand for efficient telecommunications in the era of Fifth Generation (5G) and Internet of Things (IoT) necessitates innovative approaches to network architecture and communication technologies. Recently, split Centralized Radio Access Network (C-RAN) architecture, characterized by Central Unit (CU), geographically dispersed Distributed Unit (DU), and indoor Radio Units (RUs), has presented opportunities for optimizing communication links in indoor environments. Yet, the adaptation of this innovative architecture to enable massive indoor IoT applications is still deemed inefficient due to the associated cost of deployment. Accordingly, this research investigates Power-Line Communication (PLC) as a cost-efficient alternative solution for C-RAN front-haul. Specifically, the focus is on exploring the utilization of indoor low-voltage power lines in the context of 5G New Radio (NR) indoor IoT applications. First, to ensure that standard protocols like Common Public Radio Interface (CPRI) and Enhanced Common Public Radio Interface (eCPRI) can run on PLC, we introduce two novel patented components to the architecture, namely the CPRI-PLC-Gateway (CPG) and Enhanced CPRI-PLC-Gateway (eCPG). These are a plug and play components that come in pairs. They are used to create a virtual PLC front-haul link ensuring transparent transportation of unmodified CPRI or eCPRI frames between DU and RUs, even under challenging PLC channel conditions. As such, they set the foundation for optimizing the PLC front-haul and help resolve various challenges, including PLC time-varying nature and susceptibility to additive white Gaussian noise (AWGN). Furthermore, investigations are extended to study the impact of the proposed PLC based split C-RAN system in the context of the Radio access network (RAN). For that, an indoor multi-story service building that houses a large number of air-interfaced IoT devices is considered. To ensure that the reported results apply to real-life applications, we consider a PLC network that encompasses typical indoor low-voltage 3-phase power lines and follows TN-S earthing configuration. Accordingly, it is shown that through the incorporation of the CPG and eCPG components, the implementation of In-band full-duplex (IBFD) communication over the multiple Input - multiple output (MIMO) PLC channel, and the integration of the hybrid circuit-based isolation, the system can support a considerable number of air interfaced IoT devices at standardized rates. It is also shown that the self-interference over the power line segment is mitigated which ensures robust bidirectional communication in the system. Moreover, a significant aspect of the thesis revolves around conducting a comprehensive performance analysis for the proposed PLC front-haul for IoT indoor communications. Mathematical models, rooted in queuing theory, Markov modelling, and stochastic geometry, are developed to assess the end-to-end delay performance of the indoor front-haul solution. Analytical expressions are derived for various performance metrics, including radio coverage probability, the number of served devices, and system delay. Wireless spatial models, path-loss models, and interference considerations are meticulously analysed in terms of multiple factors such as the number of wireless IoT devices, radio and PLC bandwidth, and transmission technology, in regard to the delay performance of the proposed system. These models are rigorously validated through extensive simulations, demonstrating compliance with stringent 5G, CPRI, and eCPRI bit error rate (BER) and delay requirements. Last, as the thesis further aims to examine the optimization challenge of maximizing throughput in a split-RAN system that includes a PLC front-haul link within a multi-story building. The goal is to optimize the number of fulfilled IoT devices while simultaneously satisfying their quality of service (QoS) criteria. The optimization problem is defined as a mixed-integer non-convex problem, which includes several objectives: maximizing the number of satisfied devices, minimizing operating cost, minimizing device transmit power, and minimizing PLC access delay. The thesis further explores the application of an Evolutionary Multi Objective Optimization (EMO) algorithm, specifically Non-dominated Sorting Genetic Algorithm II (NSGA-II), to address the issue of conflicting objectives in communication systems. The method operates by systematically generating successive iterations of solutions using tournament selection, single-point binary and simulated binary crossovers, and polynomial mutation operators. The system outcomes present a Pareto front consisting of non-dominated solutions for the issue defined using multi-objective optimization (MOO) showing a trade-off between the system objectives.
A Quantum Repeater Sandbox with Warm Atomic Memories and Quantum Dot Photon Sources
(University of Waterloo, 2024-09-23) Li, Michael; Bajcsy, Michal
Quantum communication is known to offer many advantages, including opportunities for distributed quantum computing and more secure information transfer through quantum key distribution. This thesis provides background on how a quantum communication network can be achieved using quantum repeaters and how these components can be constructed with a hybrid system involving a quantum dot source and warm atomic memory. It also presents three experimental projects to realize critical components to the repeater: (1) The quantum dot photon source characterizations and tuning. (2) A compact 3D printed opto-mechanical laser locking board. (3) Optical memory observed in room temperature Cs vapor cells with an EIT memory scheme. These projects have built the basic foundation to create a repeater node using room temperature vapor cells and open the doors to future investigations of warm cell experiments.
a-Si:H-Silicon Hybrid Low Energy X-ray Detector
(University of Waterloo, 2014-09-15) Shin, Kyung-Wook
Low energy X-ray (< 20 keV) detection is a key technological requirement in applications such as protein crystallography or diffraction imaging. Silicon based optical cameras based on CCDs or CMOS imaging chips coupled to X-ray conversion scintillators have become a mainstay in the field. They are attractive because of fast readout capability and ease of integrated circuit implementation due to modern semiconductor fabrication technology. More recently, hydrogenated amorphous silicon (a-Si:H) thin film technology, that had enabled a huge influx of large area display products into the commercial display market, has been introduced to digital imaging in the form of active matrix flat panel imagers (AMFPIs). Although thin film technology can enable large area X-ray imaging at a potentially lower cost, the existing technology lacks spatial resolution requirements for higher performance crystallography and diffraction imaging applications. This work introduces a high resolution direct conversion silicon X-ray detector integrated with large area thin film silicon technology for sub-20 keV photon X-ray imagers. A prototype pixel was fabricated in-house using a fabrication facility (G2N) utilizing plasma enhanced chemical vapor deposition (PECVD), reactive ion etching (RIE), photo-lithography, and metal sputtering technologies. Unlike most active matrix display products, top-gate staggered a-Si:H thin film transistor (TFT) were implemented to take advantage of a novel thin film silicon pixel amplification device architecture. The detector performance was evaluated with an iron 55 isotope gamma ray source to mimic low energy X-ray exposure. I-V and C-V measurement techniques indicate that the hybrid pixel functions as expected and is promising for low cost, high resolution, large area X-ray imaging (< 20 keV) applications. We also performed a noise spectrum investigation to estimate the lowest detection signal level limit and proposed a model rooted in device physics for the pixel output and gain.
Abstraction and Refinement Techniques for Ternary Symbolic Simulation with Guard-value Encoding
(University of Waterloo, 2022-05-20) Yang, Bo; Aagaard, Mark
We propose a novel encoding called guard-value encoding for the ternary domain {0, 1, X}. Among the advantages it has over the more conventional dual-rail encoding, the flexibility of representing X with either of <0, 0> or <0, 1> is especially important. We develop data abstraction and memory abstraction techniques based on the guard-value encoding. Our data abstraction reduces much more of the state space than conventional ternary abstraction's approach of over-approximating a set of Boolean values with a smaller set of ternary values. We also show how our data abstraction can enable bit-width reduction which helps further simplify verification problems. Our memory abstraction is applicable to any array of elements which makes it much more general than the existing memory abstraction techniques. We show how our memory abstraction can effectively reduce an array to just a few elements even when existing approaches are not applicable. We make extensive use of symbolic indexing to construct symbolic ternary values which are used in symbolic simulation. Lastly, we give a new perspective on refinement for ternary abstraction. Refinement is needed when too much information is lost due to use of the ternary domain such that the property is evaluated to the unknown X. We present a collection of new refinement approaches that distinguish themselves from existing ones by modifying the transition function instead of the initial ternary state and ternary stimulus. This way, our refinement either preserves the abstraction level or only degrades it slightly. We demonstrate our proposed techniques with a wide range of designs and properties. With data abstraction, we usually observe at least 10X improvement in verification time compared to Boolean verification algorithms such as Boolean Bounded Model Checking (BMC), as well as usually at least 2X and often 10X improvement over conventional ternary abstraction. Our memory abstraction significantly improves how the verification time scales with the design parameters and the depth (the number of cycles) of the verification. Our refinement approaches are also demonstrated to be much better than existing ones most of the time. For example, when verifying a property of a synthetic example based on a superscalar microprocessor's bypass paths, with our data abstraction, it takes 505 seconds while both of ternary abstraction and BMC time out at 1800 seconds. The bit-width reduction can further save 44 seconds and our memory abstraction can save 237 seconds. This verification problem requires refinement. If we substitute our refinement with an existing approach, the verification time with the data abstraction doubles.
Abstraction Mechanism on Neural Machine Translation Models for Automated Program Repair
(University of Waterloo, 2019-09-23) Wei, Moshi; Tan, Lin
Bug fixing is a time-consuming task in software development. Automated bug repair tools are created to fix programs with little or no human effort. There are many existing tools based on the generate-and-validate (G&V) approach, which is an automated program repair technique that generates a list of repair candidates then selects the correct candidates as output. Another approach is learning the repair process with machine learning models and then generating the candidates. One machine learning-based approach is the end-to-end approach. This approach passes the input source code directly to the machine learning model and generates the repair candidates in source code as output. There are several challenges in this approach such as the large size of vocabulary, high rate of out-of-vocabulary(OOV) tokens and difficulties on embedding learning. We propose an abstraction-and-reconstruction technique on top of end-to-end approaches that convert the training source code to templates to alleviate the problems in the traditional end-to-end approach. We train the machine learning model with abstracted bug-fix pairs from open source projects. The abstraction process converts the source code to templates before passing it to the model. After the training is complete, we use the trained model to predict the fix templates of new bugs. The output of the model is passed to the reconstruction layer to get the source code patch candidates. We train the machine learning model with 470,085 bug-fix pairs collected from 1000 top python projects from Github. We use the QuixBugs dataset as the test set to evaluate the result. The fix of the bug in the QuixBugs is verified by the test cases provided by the QuixBugs dataset. We choose the traditional end-to-end approach as the baseline and comparing it with the abstraction model. The accuracy of generating correct bug fixes increase from 25% to 57.5% while the training time reduces from 5.7 hours to 1.63 hours. The overhead introduced by the reconstruction model is 218 milliseconds on average or 23.32%, which is negligible comparing to the time saved in the training, which is 4.07 hours or 71.4%. We performed a deep analysis of the result and identified three reasons that may explain why the abstraction model outperforms the baseline. Compared to existing works, our approach has the complete reconstruction process which converts templates to the source code. It shows that adding a layer of abstractions increase the accuracy and reduces the training time of machine-learning-based automated bug repair tool.
Accelerating Mixed-Abstraction SystemC Models on Multi-Core CPUs and GPUs
(University of Waterloo, 2014-04-28) Kaushik, Anirudh Mohan
Functional verification is a critical part in the hardware design process cycle, and it contributes for nearly two-thirds of the overall development time. With increasing complexity of hardware designs and shrinking time-to-market constraints, the time and resources spent on functional verification has increased considerably. To mitigate the increasing cost of functional verification, research and academia have been engaged in proposing techniques for improving the simulation of hardware designs, which is a key technique used in the functional verification process. However, the proposed techniques for accelerating the simulation of hardware designs do not leverage the performance benefits offered by multiprocessors/multi-core and heterogeneous processors available today. With the growing ubiquity of powerful heterogeneous computing systems, which integrate multi-processor/multi-core systems with heterogeneous processors such as GPUs, it is important to utilize these computing systems to address the functional verification bottleneck. In this thesis, I propose a technique for accelerating SystemC simulations across multi-core CPUs and GPUs. In particular, I focus on accelerating simulation of SystemC models that are described at both the Register-Transfer Level (RTL) and Transaction Level (TL) abstractions. The main contributions of this thesis are: 1.) a methodology for accelerating the simulation of mixed abstraction SystemC models defined at the RTL and TL abstractions on multi-core CPUs and GPUs and 2.) An open-source static framework for parsing, analyzing, and performing source-to-source translation of identified portions of a SystemC model for execution on multi-core CPUs and GPUs.

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