A Fault Tolerant Core for Parallel Execution of Ultra Reduced Instruction Set (URISC) and MIPS Instructions

Abstract

Modern safety critical systems require the ability to detect and handle situations where an error has occurred. Efficient coding and protection schemes are widely used to protect the communication links and memories of such systems. The remaining system components, and focus of this work, are primarily computation units where most protection schemes involve a high cost by fully duplicating the computation unit. Previous work presented the Ultra Reduced Instruction Set Co-processor (URISC) core that provides a low area overhead approach to detect and recover from errors in any core computation unit (touring complete). It executes URISC or MIPS instructions in order and no more than one instruction per cycle.

This thesis analyses the overhead introduced in the previous core design to identify opportunities to accelerate the computation. We design and build an out of order core supporting both MIPS and URISC instructions. This new core effectively exploits the parallelism available in MIPS-URISC programs and significantly reduces the overhead introduced when checking or substituting URISC instructions for faulted MIPS instructions.