Optimizations and Hardware Implementations for Composited de Bruijn Sequence Generators
| dc.contributor.author | Yang, Bo | |
| dc.date.accessioned | 2016-01-21T16:33:56Z | |
| dc.date.available | 2016-01-21T16:33:56Z | |
| dc.date.issued | 2016-01-21 | |
| dc.date.submitted | 2016-01-20 | |
| dc.description.abstract | A binary de Bruijn sequence with period 2^n is a sequence in which every length-n sub-sequence occurs exactly once. de Bruijn sequences have randomness properties that make them attractive for pseudorandom number generators. Unfortunately, it is very difficult to find de Bruijn sequence generators with large periods (e.g., 2^{64}) and most known de Bruijn sequence construction techniques are computationally quite expensive. In this thesis we present a set of optimizations that reduces the computational complexity of the de Bruijn sequence generators constructed by the composited construction technique, which is the most effective one we know. We call optimized composited de Bruijn sequence generators "OcDeb". An original (k, n)-composited de Bruijn sequence generator generates a sequence with period 2^{n+k} and uses O(k^2 + nk) bit operations. Our optimizations reduce this to O(klog (k) + log (n)) operations, allow retiming, and enable parallel implementations that produce multiple bits per clock cycle while reusing some combinational hardware. Our optimizations are formulated in lemmas and theorems with proofs. The benefits of OcDeb-k-n over (k, n)-composited de Bruijn sequence generators are demonstrate by comprehensive results in a 65nm CMOS ASIC library. For example, before place-and-route, an instance of OcDeb-32-32 has a period of 2^{64}, an area of 656 GE and a maximum performance of 1.67 Gbps, representing 1.7X and 29.4X improvement on area and performance respectively over the previous implementation method presented by Mandal and Gong; with parallelization, this instance can achieve 8.30 Gbps with an area of 1229 GE. An instance of OcDeb-512-32 has a period of 2^{544}, an area of 7949 GE, and a maximum performance of 1.43 Gbps. | en |
| dc.identifier.uri | http://hdl.handle.net/10012/10181 | |
| dc.language.iso | en | en |
| dc.pending | false | |
| dc.publisher | University of Waterloo | en |
| dc.subject | de Bruijn sequences | en |
| dc.subject | Span-n sequences | en |
| dc.subject | Pseudorandom sequence generators | en |
| dc.subject | Hardware implementation | en |
| dc.title | Optimizations and Hardware Implementations for Composited de Bruijn Sequence Generators | en |
| dc.type | Master Thesis | en |
| uws-etd.degree | Master of Applied Science | en |
| uws-etd.degree.department | Electrical and Computer Engineering | en |
| uws-etd.degree.discipline | Electrical and Computer Engineering | en |
| uws-etd.degree.grantor | University of Waterloo | en |
| uws.contributor.advisor | Aagaard, Mark | |
| uws.contributor.affiliation1 | Faculty of Engineering | en |
| uws.peerReviewStatus | Unreviewed | en |
| uws.published.city | Waterloo | en |
| uws.published.country | Canada | en |
| uws.published.province | Ontario | en |
| uws.scholarLevel | Graduate | en |
| uws.typeOfResource | Text | en |