Monolithic RF frequency synthesis for wireless communications

Abstract

The increasing demand for a small sized, low cost wireless transceivers with a long battery life calls for a move towards higher levels of integration. However, the design of the frequency synthesizer hinders the development of a fully integrated wireless radio, because of the stringent phase noise requirements for both the transmit and receive synthesizers. Moreover, the synthesizers require fast switching speeds, low spur levels, and reduced sensitivity to interference caused by other components sharing the same power supply and/or substrate. Unlike other radio components, the synthesizer is active most of the time. Therefore, minimizing its power consumption is critical for a longer battery life.

Traditionally, the VCO has dominated the phase noise in the design of the frequency synthesizer. The key has been the use of an off-chip VCO module with high Q discrete resonators to realize the low phase noise requirement. The lack of high Q integrated resonators constitutes a major challenge towards integrating the VCO. Also, applications of integrated VCO's are limited, due to the large fabrication tolerances in the integrated varactor values. Consequently, a wide VCO tuning range is needed to cover the process variations, using only a limited control voltage range. However, this high tuning sensitivity exposes the VCO to more noise pick up.

The objective of this thesis is to provide both circuit and system level solutions to enhance the performance of integrated frequency synthesizers. On the circuit level, two VCO architectures are presented, to reduce the VCO phase noise, as well as its sensitivity to noise pick up. A fully differential PLL (including the VCO) is integrated on a single chip in a 0.5 micron CMOS process. The differential architecture reduces the circuit sensitivity to both supply and substrate noise. A novel technique is used to differentially control the LC VCO without sacrificing the tuning range. The measured VCO phase noise is -119 dBc at 1MHz offset, and its tuning range is 26% around its 1.25 GHz center frequency. The PLL in-band phase noise is -96 dBc with a total power consumption of 13.6 mA from ma 3 V supply.

In order to reduce the VCOphase noise, we propose a VCO architecture based on coupled tank resonators. The coupled tanks provide a higher frequency selectivity, that reduces the phase noise. The phase noise is further reduced by cascading four of these resonators in a ring VCO structure, that provides accurate quadrature outputs. The proposed VCO is designed in a 0.35 micron CMOS technology, and achieves a phase noise as low as -122 dBc at 600 kHz offset from a 1.93 GHz oscillator center frequency with a current consumption of 9.2 mA. This phase noise is significantly better than other I-Q VCO implementations reported in the literature with similar power consumption.

On the synthesizer system architecture level, many researche4rs have proposed the use of wide band PLLs to relax the VCO phase noise requirements. Not only does this ease the VCO design, but also increases the synthesizer switching speed. Fractional-N frequency division is a very popular way to increase the PLL loop band width without changing the channel spacing. Following this trend, we pursue a detailed circuit level implementation of a factional-N synthesizer with an on chip spur compensation. This compensation technique relies on a digitally controlled delay to shift the fractional divider output so that no phase error is produced. Even though this technique has theoretically, no systematic error, circuit level simulations do show high levels of fractional spurs. It seems that a more drastic system architecture change is required.

Therefore, we present a phase domain fractional-N frequency synthesizer architecture that achieves high switching speeds and a very narrow channel spacing. In this architecture, a numerical phase comparator is used as a linear Weighted Phase Frequency Detector. The output spur level is limited by the delay of the numerical phase comparator, and the accuracy of the DAC used to convert the phase error to the analog domain. A novel timing error cancelation scheme that is capable of eliminating the effect of the phase comparator delays, is proposed With this technique and a 10-bit accuracy DAC, the simulated spur level is as low as -65 dBc. The settling time is less than 7 us, and is independent of the channel spacing. The advantages of the synthesizer architecture, design considerations, and system level simulations are discussed.