A Link-Level Communication Analysis for Real-Time NoCs

dc.contributor.authorGholamian, Sina
dc.date.accessioned2012-08-29T16:15:11Z
dc.date.available2012-08-29T16:15:11Z
dc.date.issued2012-08-29T16:15:11Z
dc.date.submitted2012
dc.description.abstractThis thesis presents a link-level latency analysis for real-time network-on-chip interconnects that use priority-based wormhole switching. This analysis incorporates both direct and indirect interferences from other traffic flows, and it leverages pipelining and parallel transmission of data across the links. The resulting link-level analysis provides a tighter worst-case upper-bound than existing techniques, which we verify with our analysis and simulation experiments. Our experiments show that on average, link-level analysis reduces the worst-case latency by 28.8%, and improves the number of flows that are schedulable by 13.2% when compared to previous work.en
dc.identifier.urihttp://hdl.handle.net/10012/6906
dc.language.isoenen
dc.pendingfalseen
dc.publisherUniversity of Waterlooen
dc.subjectNetwork-on-Chipen
dc.subjectReal-Timeen
dc.subject.programElectrical and Computer Engineeringen
dc.titleA Link-Level Communication Analysis for Real-Time NoCsen
dc.typeMaster Thesisen
uws-etd.degreeMaster of Applied Scienceen
uws-etd.degree.departmentElectrical and Computer Engineeringen
uws.peerReviewStatusUnrevieweden
uws.scholarLevelGraduateen
uws.typeOfResourceTexten

Files

Original bundle

Now showing 1 - 1 of 1
Loading...
Thumbnail Image
Name:
Gholamian_Sina.pdf
Size:
4.54 MB
Format:
Adobe Portable Document Format

License bundle

Now showing 1 - 1 of 1
No Thumbnail Available
Name:
license.txt
Size:
253 B
Format:
Item-specific license agreed upon to submission
Description: