RRAM in High-speed TCAM Design and Its Applications with New Switching Materials

Abstract

With the continuous scaling of transistor devices reaching their physical limits, emerging non-volatile memory (eNVM) devices such as resistive random-access memory (RRAM) is considered one of the alternatives to maintain growth in semiconductor technology as predicted by Moore's law. Meanwhile, it is becoming difficult for the traditional von Neuman architecture to meet the continuous growing demand of computation power in integrated circuit (IC) applications. New data processing scheme such as neuromorphic network are attracting great interests in both research and industry. RRAM, as a type of eNVM and resistive switching device, possesses the advantages of compact size, high switching speed, low programming voltage, large ON/OFF resistance ratio and compatibility with current complementary metal-oxide-semiconductor (CMOS) fabrication process. It has been studied extensively in implementing large scale random-access memory (RAM) array and artificial neural networks (ANNs). In this thesis, a novel RRAM-based circuit is presented to achieve high density and highly energy efficient memory system, with tunable delay element (TDE) for reference signal generation. A parallel-RRAM structure is proposed to address the serious issue of RRAM intra-cell and inter-cell switching variations in terms of programming voltage and resultant resistance after the programming process. RRAM-based neuromorphic network is also explored through device and circuit level innovations.

For the RRAM-based memory system, a current race (CR)-based ternary content addressable memory (TCAM) circuit design is proposed using RRAM technology. The suggested design adopts a match-line (ML) booster feature in sensing amplifier to improve search speed and tolerance to RRAM switching variations. Two cascading schemes, direct cascading (DC) and SR-latch cascading (SRC), are proposed to further improve performance and energy efficiency for large TCAM array. The DC structure features high noise margin while SRC structure improves search speed. Additionally, a same clock phase cascading (SCPC) scheme is proposed to reduce latency in cascading structure, by placing evaluation phase of all stages in the same clock phase. With the suggested ML booster, the 64-bit 1-stage design has speed and energy consumption matching the best performance reported by other eNVM-based TCAM design. The proposed 128-bit 2-stage design also has comparable speed and energy to SRAM-based TCAM design with significantly more compact size (90% reduction) and non-volatility.

Meanwhile, a TDE design with delay range from ~100ps to ~1ns is proposed, which can be used in TCAM design for reference signal generation. Impacts of RRAM resistance on delay range and power consumption of the circuit are analyzed. An improved parallel RRAM TDE circuit is also proposed to reduce impact of switching variation of RRAM device and provide finer tunable delay resolution.

The last part of this study is focusing on RRAM-based neuromorphic networks, two RRAM devices are presented and reviewed: Al2O3-based and CuZnSe (CZSe)-based. The capacitive-coupled Al2O3-based RRAM is used in design simulation of a leaky-integrate and fire (LIF) neuron circuit. It can provide post-fabrication tunability of leakage rate, improving flexibility of circuit design. The CZSe-based device demonstrates concurrent resistive switching and light activated conduction effect. Its synaptic behavior is investigated and used in simulating an ANN for pattern recognition. The simulated results indicate high output accuracy from the ANN.