ReserveTM: Optimizing for Eager Software Transactional Memory
| dc.contributor.author | Jain, Gaurav | |
| dc.date.accessioned | 2013-09-26T16:36:17Z | |
| dc.date.available | 2013-09-26T16:36:17Z | |
| dc.date.issued | 2013-09-26T16:36:17Z | |
| dc.date.submitted | 2013 | |
| dc.description.abstract | Software Transactional Memory (STM) helps programmers write correct concurrent code by allowing them to identify atomic sections rather than focusing on the mechanics of concurrency control. Given code with atomic sections, the compiler and STM runtime can work together to ensure proper controlled access to shared memory. STM runtimes use either lazy or eager version management. Lazy versioning buffers transaction updates, whereas eager versioning applies updates in-place. The current set of primitives suit lazy versioning since memory needs to be accessed through the runtime. We present a new set of runtime primitives that better suit eager versioned STM. We propose a novel extension to the compiler/runtime interface, consisting of memory reservations and memory releases. These extensions enable optimizations specific to eager versioned runtimes. A memory reservation allows a transaction to perform instrumentation-free access on a memory address. A release allows a read-only address to be modified by another transaction. Together, these reduce the instrumentation overhead required to support STM and improve concurrency between readers and writers. We have implemented these primitives and evaluated its performance on the STAMP benchmarks. Our results show strong performance and scalability improvements to eager versioned algorithms. | en |
| dc.identifier.uri | http://hdl.handle.net/10012/7921 | |
| dc.language.iso | en | en |
| dc.pending | false | en |
| dc.publisher | University of Waterloo | en |
| dc.subject | Software Transactional Memory | en |
| dc.subject | Memory reservations | en |
| dc.subject | memory releases | en |
| dc.subject | privatization | en |
| dc.subject | eager versioning | en |
| dc.subject | TM API design | en |
| dc.subject.program | Electrical and Computer Engineering | en |
| dc.title | ReserveTM: Optimizing for Eager Software Transactional Memory | en |
| dc.type | Master Thesis | en |
| uws-etd.degree | Master of Applied Science | en |
| uws-etd.degree.department | Electrical and Computer Engineering | en |
| uws.peerReviewStatus | Unreviewed | en |
| uws.scholarLevel | Graduate | en |
| uws.typeOfResource | Text | en |