A High Performance DDR4 Memory Controller on FPGA

Abstract

We introduce a high-performance DDR4 SDRAM memory controller synthesizable design for AMD/Xilinx's FPGA devices. Due to limitations in operating frequency, the design on FPGA presents additional challenges compared to ASIC: in particular, the controller must be able to issue 4 DRAM commands in a single clock cycle. Utilizing Xilinx's memory controller (MIG) as a foundational framework, our design incorporates features such as the discrimination of received requests based on their origin and the implementation of the FR-FCFS arbitration scheme in the front-end scheduler. Additionally, our memory controller utilizes the Round Robin arbitration scheme in the back-end scheduler to optimize throughput through effective bank parallelism. Our memory controller is able to perform DRAM initialization, refresh, and calibration. Its design is extensible, allowing for further development of other types of DDR4 memory controllers and adaptation for various DDR4 speed grades. To evaluate the performance of our memory controller and Xilinx's MIG, we conducted extensive assessments using both realistic and synthetic traces in simulation. The obtained results provide a comprehensive comparison of their performance across various scenarios, offering valuable insights for further developments in the field.