Worst Case Analysis of DRAM Latency in Hard Real Time Systems
| dc.contributor.author | Wu, Zheng Pei | |
| dc.date.accessioned | 2013-12-17T21:22:15Z | |
| dc.date.available | 2013-12-17T21:22:15Z | |
| dc.date.issued | 2013-12-17 | |
| dc.date.submitted | 2013-12-17 | |
| dc.description.abstract | As multi-core systems are becoming more popular in real time embedded systems, strict timing requirements for accessing shared resources must be met. In particular, a detailed latency analysis for Double Data Rate Dynamic RAM (DDR DRAM) is highly desirable. Several researchers have proposed predictable memory controllers to provide guaranteed memory access latency. However, the performance of such controllers sharply decreases as DDR devices become faster and the width of memory buses is increased. Therefore, a novel and composable approach is proposed that provides improved latency bounds compared to existing works by explicitly modeling the DRAM state. In particular, this new approach scales better with increasing number of cores and memory speed. Benchmark evaluation results show up to a 45% improvement in the worst case task execution time compared to a competing predictable memory controller for a system with 16 cores. | en |
| dc.identifier.uri | http://hdl.handle.net/10012/8099 | |
| dc.language.iso | en | en |
| dc.pending | false | |
| dc.publisher | University of Waterloo | en |
| dc.subject | WCET | en |
| dc.subject | DRAM | en |
| dc.subject | Timing Analysis | en |
| dc.subject | Hard Real Time | en |
| dc.subject.program | Electrical and Computer Engineering | en |
| dc.title | Worst Case Analysis of DRAM Latency in Hard Real Time Systems | en |
| dc.type | Master Thesis | en |
| uws-etd.degree | Master of Applied Science | en |
| uws-etd.degree.department | Electrical and Computer Engineering | en |
| uws.peerReviewStatus | Unreviewed | en |
| uws.scholarLevel | Graduate | en |
| uws.typeOfResource | Text | en |