Energy Efficient Techniques For Algorithmic Analog-To-Digital Converters
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Date
2011-12-20T14:27:11Z
Authors
Hai, Noman
Journal Title
Journal ISSN
Volume Title
Publisher
University of Waterloo
Abstract
Analog-to-digital converters (ADCs) are key design blocks in
state-of-art image, capacitive, and biomedical sensing applications.
In these sensing applications, algorithmic ADCs are the preferred
choice due to their high resolution and low area advantages.
Algorithmic ADCs are based on the same operating principle as that
of pipelined ADCs. Unlike pipelined ADCs where the residue is
transferred to the next stage, an N-bit algorithmic ADC utilizes the
same hardware N-times for each bit of resolution. Due to the
cyclic nature of algorithmic ADCs, many of the low power techniques
applicable to pipelined ADCs cannot be
directly applied to algorithmic ADCs. Consequently, compared to those of
pipelined ADCs, the traditional implementations of algorithmic ADCs are
power inefficient.
This thesis presents two novel energy efficient techniques for algorithmic
ADCs. The first technique modifies the capacitors' arrangement of a
conventional flip-around configuration and amplifier sharing
technique, resulting in a low power and low area design solution. The
other technique is based on the unit
multiplying-digital-to-analog-converter approach. The proposed
approach exploits the power saving advantages of capacitor-shared technique
and capacitor-scaled technique. It is shown that, compared to
conventional techniques, the proposed techniques reduce the
power consumption of algorithmic ADCs by more than 85\%.
To verify the effectiveness of such approaches, two
prototype chips, a 10-bit 5 MS/s and a 12-bit 10 MS/s ADCs, are
implemented in a 130-nm CMOS process. Detailed design considerations
are discussed as well as the simulation and measurement results. According to the
simulation results, both designs achieve figures-of-merit of approximately 60 fJ/step,
making them some of the most power efficient ADCs to date.
Description
Keywords
Analog-to-digital Converters, Algorithmic ADC, Pipelined ADC, Capacitor Sharing Technique, Capacitor Scaling Technique, low power, CMOS, Energy efficient