Bimodal Gate Oxide Breakdown in Sub-100 nm CMOS Technology
| dc.comment.hidden | I have revised the thesis based on the following e-mail: The Collection administrator Trevor Clews(tclews@uwaterloo.ca) has not added your submission to the archive for the following reason: Hi Please do not reply to this email. Thank you for submitting your thesis. The format has been reviewed and problems have been noted below. Please make the revisions and resubmit your thesis. If you have not already done so please complete and submit; a Thesis Non-Exclusive Licence, to the Graduate Studies Office, Needles Hall, Room 2201. This form is available for you to print from: http://www.collectionscanada.ca/obj/s4/f2/frm-nl59-2.pdf 1. Title page - adjust the line that reads 'Waterloo, Ontario, Canada, December 2008' to appear as 'Waterloo, Ontario, Canada, 2008'. Below this line add '© Leila Rezaee 2008'. (Note: do not include commas in the copyright line) 2. Author's declaration - must ONLY read: I hereby declare that I am the sole author of this thesis. This is a true copy of the thesis, including any required final revisions, as accepted by my examiners. I understand that my thesis may be made electronically available to the public. 3. Table of contents - remove the Abstract, Acknowledgements, and Contents title from the Table of contents list. 4. Table of contents - add an Appendices title above the Bibliography to the Table of contents list. Thank you Trevor | en |
| dc.contributor.author | Rezaee, Leila | |
| dc.date.accessioned | 2008-12-19T19:14:46Z | |
| dc.date.available | 2008-12-19T19:14:46Z | |
| dc.date.issued | 2008-12-19T19:14:46Z | |
| dc.date.submitted | 2008-12-08 | |
| dc.description.abstract | In the last three decades, the electronic industry has registered a tremendous progress. The continuous and aggressive downsizing of the transistor feature sizes (CMOS scaling) has been the main driver of the astonishing growth and advancement of microelectronic industry. Currently, the CMOS scaling is almost reaching its limits. The gate oxide is now only a few atomic layers thick, and this extremely thin oxide causes a huge leakage current through the oxide. Therefore, a further reduction of the gate oxide thickness is extremely difficult and new materials with higher dielectric constant are being explored. However, the phenomena of oxide breakdown and reliability are still serious issues in these thin oxides. Oxide breakdown exhibits a soft breakdown behavior at low voltages, and this is posing as one of the most crucial reliability issues for scaling of the ultra-thin oxides. In addition, the stress-induced leakage current (SILC) due to oxide has emerged as a scaling problem for the non-volatile memory technologies. In this dissertation, a percolation modeling approach is introduced to study and understand the dramatic changes in the conductivity of a disordered medium. Two different simulation methods of percolative conduction, the site and bond percolation, are studied here. These are used in simulating the post-breakdown conduction inside the oxide. Adopting a Monte-Carlo method, oxide breakdown is modeled using a 2-D percolation theory. The breakdown statistics and post-breakdown characteristics of the oxide are computed using this model. In this work, the effects of different physical parameters, such as dimension and the applied stress are studied. The simulation results show that a thinning of oxide layer and increasing the oxide area result in softening of breakdown. It is observed that the breakdown statistics appear to follow Weibull characteristics. As revealed by simulations, the Weibull slope changes linearly with oxide thickness, while not having a significant change when the area is varied and when the amount of the applied stress is varied. It is shown that the simulation results are well correlated with the experimental data reported in the literature. In this thesis, studying the conduction through the oxide using percolation model, it was discovered that a critical or a quasi-critical phenomenon occurs depending on the oxide dimensions. The criticality of the phase-transition results in a hard breakdown while the soft breakdown occurs due to a quasi-critical nature of percolation for ultra-thin oxides. In the later part of the thesis, a quantum percolation model is studied in order to explain and model the stress induced leakage current. It is explained that due to the wave nature of electrons, the SILC can be modeled as a tunneling path through the stressed oxide with the smaller tunneling threshold compared to the virgin oxide. In addition to the percolation model, a Markov chain theory is introduced to simulate the movement of electron as a random walk inside the oxide, and the breakdown is simulated using this random-walk of electron through the accumulated traps inside the oxide. It is shown that the trapping-detrapping of electrons results in an electrical noise in the post-breakdown current having 1/f noise characteristics. Using simulation of a resistor network with Markov theory, the conductance of the oxide is computed. An analytical study of a 2-D site percolation system is conducted using recursive methods and useful closed-form expressions are derived for specialized networks. | en |
| dc.identifier.uri | http://hdl.handle.net/10012/4155 | |
| dc.language.iso | en | en |
| dc.pending | false | en |
| dc.publisher | University of Waterloo | en |
| dc.subject | Oxide Breakdown | en |
| dc.subject | Percolation | en |
| dc.subject | CMOS | en |
| dc.subject | TDDB | en |
| dc.subject | CVS | en |
| dc.subject | CCS | en |
| dc.subject | SILC | en |
| dc.subject | Stress Induced Leakage Current | en |
| dc.subject | Markov Chain | en |
| dc.subject | Noise | en |
| dc.subject | Post-breakdown Current | en |
| dc.subject | Soft Breakdown | en |
| dc.subject | Hard Breakdown | en |
| dc.subject | Weibull | en |
| dc.subject | Critical Phenomenon | en |
| dc.subject | Quasi-critical Phenomenon | en |
| dc.subject | Analytical | en |
| dc.subject | Percolation Probability | en |
| dc.subject | Reliability | en |
| dc.subject | Monte-Carlo | en |
| dc.subject.program | Electrical and Computer Engineering | en |
| dc.title | Bimodal Gate Oxide Breakdown in Sub-100 nm CMOS Technology | en |
| dc.type | Doctoral Thesis | en |
| uws-etd.degree | Doctor of Philosophy | en |
| uws-etd.degree.department | Electrical and Computer Engineering | en |
| uws.peerReviewStatus | Unreviewed | en |
| uws.scholarLevel | Graduate | en |
| uws.typeOfResource | Text | en |