Combining High-Level-Synthesis and Register-Transfer Level Design for Programmable Hardware

Abstract

As network speeds continue to grow to hundreds of Gbps and beyond, offloading transport-layer functionality to programmable Network Interface Cards (NICs) has gained traction for improving performance and enabling higher-level offloads. FPGAs on NICs offer low latency and high throughput but are notoriously difficult to program. To reduce developer effort for hardware transport, prior works propose hardware architectures with reusable fixed-function modules for common transport data structures and operations, and programmable modules for protocol-specific operations. However, they either still require intricate Verilog programming for their programmable modules or are tied to specific protocols or pipeline abstractions.

In this work, we explore the design of a programmable hardware architecture for transport, called HTraP, that (1) offers a simple, intuitive programming interface without requiring detailed understanding of the rest of the architecture for effective programming, and (2) supports a broad range of transport protocols with varying levels of complexity. HTrap has one main programmable module that can be programmed to capture the core protocol logic in simple C code that is amenable to automated, efficient hardware generation with HLS. The generated hardware can then plug into the rest of HTraP which implements complex transport operations through a protocol-agnostic interface.