Side Channel Information Leakage: Design and Implementation of Hardware Countermeasure
| dc.contributor.author | Khatib Zadeh, Amirali | |
| dc.date.accessioned | 2010-01-21T22:07:12Z | |
| dc.date.available | 2015-05-01T05:30:34Z | |
| dc.date.issued | 2010-01-21T22:07:12Z | |
| dc.date.submitted | 2010-01-18 | |
| dc.description.abstract | Deployment of Dynamic Differential Logics (DDL) appears to be a promising choice for providing resistance against leakage of side channel information. However, the resistance provided by these logics is too costly for widespread area-constrained applications. Implementation of a secure DDL-based countermeasure also requires a complex layout methodology for balancing the load at the differential outputs. This thesis, unlike previous logic level approaches, presents a novel exploitation of static and single-ended logic for designing the side channel countermeasure. The proposed technique is used in the implementation of a protected crypto core consisting of the AES “AddRoundKey” and “SubByte” transformation. The test chip including the protected and unprotected crypto cores is fabricated in 180nm CMOS technology. A correlation analysis on the unprotected core results in revealing the key at the output of the combinational networks and the registers. The quality of the measurements is further improved by introducing an enhanced data capturing method that inserts a minimum power consuming input as a reference vector. In comparison, no key-related information is leaked from the protected core even with an order of magnitude increase in the number of averaged traces. For the first time, fabricated chip results are used to validate a new logic level side channel countermeasure that offers lower area and reduced circuit design complexity compared to the DDL-based countermeasures. This thesis also provides insight into the side channel vulnerability of cryptosystems in sub-90nm CMOS technology nodes. In particular, data dependency of leakage power is analyzed. The number of traces to disclose the key is seen to decrease by 35% from 90nm to 45nm CMOS technology nodes. Analysis shows that the temperature dependency of the subthreshold leakage has an important role in increasing the ability to attack future nanoscale crypto cores. For the first time, the effectiveness of a circuit-based leakage reduction technique is examined for side channel security. This investigation demonstrates that high threshold voltage transistor assignment improves resistance against information leakage. The analysis initiated in this thesis is crucial for rolling out the guidelines of side channel security for the next generation of Cryptosystem. | en |
| dc.description.embargoterms | 1 year | en |
| dc.identifier.uri | http://hdl.handle.net/10012/4967 | |
| dc.language.iso | en | en |
| dc.pending | true | en |
| dc.publisher | University of Waterloo | en |
| dc.subject | Side Channel Information | en |
| dc.subject | Countermeasure | en |
| dc.subject.program | Electrical and Computer Engineering | en |
| dc.title | Side Channel Information Leakage: Design and Implementation of Hardware Countermeasure | en |
| dc.type | Doctoral Thesis | en |
| uws-etd.degree | Doctor of Philosophy | en |
| uws-etd.degree.department | Electrical and Computer Engineering | en |
| uws.peerReviewStatus | Unreviewed | en |
| uws.scholarLevel | Graduate | en |
| uws.typeOfResource | Text | en |