Second-Generation Stack Computer Architecture

Abstract

It is commonly held in current computer architecture literature that stack-based computers were entirely superseded by the combination of pipelined, integrated microprocessors and improved compilers. While correct, the literature omits a second, new generation of stack computers that emerged at the same time. In this thesis, I develop historical, qualitative, and quantitative distinctions between the first and second generations of stack computers. I present a rebuttal of the main arguments against stack computers and show that they are not applicable to those of the second generation. I also present an example of a small, modern stack computer and compare it to the MIPS architecture. The results show that second-generation stack computers have much better performance for deeply nested or recursive code, but are correspondingly worse for iterative code. The results also show that even though the stack computer’s zero-operand instruction format only moderately increases the code density, it significantly reduces instruction memory bandwidth.