Mixed signal design flow, a mixed signal PLL case study
| dc.contributor.author | Shariat Yazdi, Ramin | en |
| dc.date.accessioned | 2006-08-22T13:47:26Z | |
| dc.date.available | 2006-08-22T13:47:26Z | |
| dc.date.issued | 2001 | en |
| dc.date.submitted | 2001 | en |
| dc.description.abstract | Mixed-signal designs are becoming more and more complex every day. In order to adapt to the new market requirements, a formal process for design and verification of mixed signal systems i. e. top-down design and bottom-up verification methodology is required. This methodology has already been established for digital design. The goal of this research is to propose a new design methodology for mixed signal systems. In the first two chapters of this thesis, the need for a mixed signal design flow based on top-down design methodology will be discussed. The proposed design flow is based on behavioral modeling of the mixed signal system using one of the mixed signal behavioral modeling languages. These models can be used for design and verification through different steps of the design from system level modeling to final physical design. The other advantage of the proposed flow is analog and digital co-design. In the remaining chapters of this thesis, the proposed design flow was verified by designing an 800 MHz mixed signal PLL. The PLL uses a charge pump phase frequency detector, a single capacitor loop filter, and a feed forward error correction architecture using an active damping control circuit instead of passive resistor in loop filter. The design was done in 0. 18- <i>ยต</i> m CMOS process technology. | en |
| dc.format | application/pdf | en |
| dc.format.extent | 1028268 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.identifier.uri | http://hdl.handle.net/10012/916 | |
| dc.language.iso | en | en |
| dc.pending | false | en |
| dc.publisher | University of Waterloo | en |
| dc.rights | Copyright: 2001, Shariat Yazdi, Ramin. All rights reserved. | en |
| dc.subject | Electrical & Computer Engineering | en |
| dc.subject | mixed signal design flow | en |
| dc.subject | behavioral modeling | en |
| dc.subject | phase locked loops | en |
| dc.title | Mixed signal design flow, a mixed signal PLL case study | en |
| dc.type | Master Thesis | en |
| uws-etd.degree | Master of Applied Science | en |
| uws-etd.degree.department | Electrical and Computer Engineering | en |
| uws.peerReviewStatus | Unreviewed | en |
| uws.scholarLevel | Graduate | en |
| uws.typeOfResource | Text | en |
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