Optimizations of Cisco’s Embedded Logic Analyzer Module
| dc.contributor.author | Yang, Fangjin | |
| dc.date.accessioned | 2009-07-24T13:55:16Z | |
| dc.date.available | 2009-07-24T13:55:16Z | |
| dc.date.issued | 2009-07-24T13:55:16Z | |
| dc.date.submitted | 2009 | |
| dc.description.abstract | Cisco’s embedded logic analyzer module (ELAM) is a debugging device used for many of Cisco’s application specific integrated chips (ASICs). The ELAM is used to capture data of interest to the user and stored for analysis purposes. The user enters a trigger expression containing data fields of interest in the form of a logical equation. The data fields associated with the trigger expression are stored in a set of Match and Mask (MM) registers. Incoming data packets are matched against these registers, and if the user-specified data pattern is detected, the ELAM triggers and begins a countdown sequence to stop data capture. The current ELAM implementation is restricted in the form of trigger expressions that are allowed and in the allocation of resources. Currently, data fields in the trigger expression can only be logically ANDed together, Match and Mask registers are inefficiently utilized, and a static state machine exists in the ELAM trigger logic. To optimize the usage of the ELAM, a trigger expression is first treated as a Boolean expression so that minimization algorithms can be run. Next, the data stored in the Match and Mask registers is analyzed for redundancies. Finally, a dynamic state machine is programmed with a distinct set of states generated from the trigger expression. This set of states is further minimized. A feasibility study is done to analyze the validity of the results. | en |
| dc.identifier.uri | http://hdl.handle.net/10012/4516 | |
| dc.language.iso | en | en |
| dc.pending | false | en |
| dc.publisher | University of Waterloo | en |
| dc.subject | Cisco | en |
| dc.subject | logic minimization | en |
| dc.subject.program | Electrical and Computer Engineering | en |
| dc.title | Optimizations of Cisco’s Embedded Logic Analyzer Module | en |
| dc.type | Master Thesis | en |
| uws-etd.degree | Master of Applied Science | en |
| uws-etd.degree.department | Electrical and Computer Engineering | en |
| uws.peerReviewStatus | Unreviewed | en |
| uws.scholarLevel | Graduate | en |
| uws.typeOfResource | Text | en |