Load Variation Resilient and Average Efficiency Enhanced Power Amplifiers for 5G/6G Beamforming System

Abstract

The deployment of Fifth Generation (5G) and Sixth Generation (6G) infrastructure relies heavily on high-frequency beamforming architectures to deliver high data rates and spectral efficiency. However, the physical realization of these systems faces critical challenges: the need for high circuit integration, energy efficiency under high Peak-to-Average Power Ratio (PAPR) signals, and robustness against dynamic load variations inherent in large-scale arrays. This doctoral thesis addresses these requirements through the development of three advanced integrated circuit objectives, progressing from theoretical derivations in load variation resiliency (Voltage-Standing-Wave-Ratio (VSWR) resiliency) to front-end architectural synthesis for Power Amplifiers (PAs).

To improve circuit integration and performance for Time-Division Duplex (TDD) operation in beamforming systems, Chapter 3 focuses on the co-design of a Transmit/Receive (T/R) Front-End Module (FEM). Traditional FEMs suffer from insertion loss and area overhead due to additional Single-Pole Double-Throw (SPDT) switches. To resolve this, this work presents an architecture that integrates a Doherty Power Amplifier (DPA) in the transmit path, which also functions as a switchless T/R isolation network during receive operation. On the receiver side, an embedded switching network maximizes isolation and bandwidth while jointly optimizing the overall FEM performance and integration trade-offs. A 39 GHz prototype was fabricated using the GlobalFoundries 45nm Silicon-On-Insulator (SOI) CMOS process and achieves a Transmit (TX) mode gain of 15 dB, a saturated output power of 20 dBm, and a Power-Added Efficiency (PAE) of 23%/15% at peak and 6-dB back-off, respectively. In Receive (RX) mode, it delivers 20 dB of gain, a 4.5-dB noise figure, and an input 1-dB compression power of -16.5 dBm while consuming 32 mW. Occupying a core area of just 0.5 x 0.75 mm^2, this architecture demonstrates a highly competitive efficiency-noise-integration trade-off, achieving state-of-the-art performance for high-frequency FEMs.

While integration and performance improvements are critical for beamforming systems, the load variation induced by antenna mutual coupling in Large-Scale Antenna Arrays (LSAAs) presents another critical challenge. Chapter 4 proposes a dual-mode PA design, utilizing different gate biasing to reconfigure its operational state. The work features a 'VSWR resiliency mode' to maintain robust performance under high load mismatch, and an 'Output-Back-Off (OBO) efficiency enhancement mode' to maximize efficiency under minimal load variation. Central to this design is a novel combiner network synthesized to support two distinct operational regimes: it can emulate the characteristics of balanced architectures (symmetric drain currents) for load-variation resiliency, or Doherty load modulation (asymmetric drain currents) for efficient OBO operation. A 29 GHz prototype was fabricated using GlobalFoundries' 22nm Fully-Depleted SOI CMOS process to validate the concept. Under a 50-ohm load, the VSWR-resilient mode achieves 16.5-dB gain, 12.5-dBm output power, and 18%/7.5% PAE at peak/6-dB OBO. The OBO efficiency-enhanced mode delivers 13-dBm output power with 19%/12.5% PAE at peak/6-dB OBO. Across a load of 2.5:1 VSWR over a 360-degree phase range, the VSWR-resilient mode exhibits only 0.5-dB average saturated-power degradation compared to 1~dB in the OBO efficiency-enhanced mode. Modulated measurements under varying VSWR loads further confirm the superior load-variation tolerance of the proposed architecture.

The above-mentioned dual-mode approach offers flexibility between VSWR resiliency and efficiency improvements; however, communication protocols often demand simultaneous efficient and robust operation. Consequently, Chapter 5 unifies these requirements by establishing the theory and design of a "VSWR-Resilient DPA," extending the analytical framework of Chapter 4 to ensure robust performance across multiple power regimes. The analysis yields architectures that maintain the OBO efficiency profile of a DPA while simultaneously delivering load-variation insensitivity against Multiple-Input-Multiple-Output (MIMO) beamforming array mismatch. A prototype targeting 8 GHz is designed using a commercial MACOM GaN bare-die transistor on a multi-layer PCB substrate; however, due to procurement delays, experimental validation is deferred to future work. In EM circuit co-simulation, the architecture achieves 10-dB SS gain, 45-dBm saturated output power, and 49%/35% PAE at peak/6-dB OBO under a 50-ohm load, while maintaining less than 1.5-dBm saturated power variation and 1.55× normalized Class-B efficiency at 6-dB OBO across different antenna loads on the 3:1 VSWR circle.