Strong Induction in Hardware Model Checking
dc.contributor.author | Vediramana Krishnan, Hari Govind | |
dc.date.accessioned | 2019-08-14T20:00:33Z | |
dc.date.available | 2019-08-14T20:00:33Z | |
dc.date.issued | 2019-08-14 | |
dc.date.submitted | 2019-08-12 | |
dc.description.abstract | Symbolic Model checking is a widely used technique for automated verification of both hardware and software systems. Unbounded SAT-based Symbolic Model Checking (SMC) algorithms are very popular in hardware verification. The principle of strong induction is one of the first techniques for SMC. While elegant and simple to apply, properties as such can rarely be proven using strong induction and when they can be strengthened, there is no effective strategy to guess the depth of induction. It has been mostly displaced by techniques that compute inductive strengthenings based on interpolation and property directed reachability (PDR). In this thesis, we prove that strong induction is more concise than induction. We then present kAvy, an SMC algorithm that effectively uses strong induction to guide interpolation and PDR-style incremental inductive invariant construction. Unlike pure strong induction, kAvy uses PDR-style generalization to compute and strengthen an inductive trace. Unlike pure PDR, kAvy uses relative strong induction to construct an inductive invariant. The depth of induction is adjusted dynamically by minimizing a proof of unsatisfiability. We have implemented kAvy within the Avy Model Checker and evaluated it on HWMCC instances. Our results show that kAvy is more effective than both Avy and PDR, and that using strong induction leads to faster running time and solving more instances. Further, on a class of benchmarks, called shift, kAvy is orders of magnitude faster than Avy, PDR and pure strong induction. | en |
dc.identifier.uri | http://hdl.handle.net/10012/14885 | |
dc.language.iso | en | en |
dc.pending | false | |
dc.publisher | University of Waterloo | en |
dc.subject | model checking | en |
dc.subject | formal methods | en |
dc.subject | formal verification | en |
dc.subject | hardware verification | en |
dc.title | Strong Induction in Hardware Model Checking | en |
dc.type | Master Thesis | en |
uws-etd.degree | Master of Applied Science | en |
uws-etd.degree.department | Electrical and Computer Engineering | en |
uws-etd.degree.discipline | Electrical and Computer Engineering | en |
uws-etd.degree.grantor | University of Waterloo | en |
uws.contributor.advisor | Gurfinkel, Arie | |
uws.contributor.advisor | Ganesh, Vijay | |
uws.contributor.affiliation1 | Faculty of Engineering | en |
uws.peerReviewStatus | Unreviewed | en |
uws.published.city | Waterloo | en |
uws.published.country | Canada | en |
uws.published.province | Ontario | en |
uws.scholarLevel | Graduate | en |
uws.typeOfResource | Text | en |