Safe Memory Reclamation Techniques

Abstract

This dissertation presents three paradigms to address the challenge of concurrent memory reclamation, manifesting as use-after-free errors that arise in concurrent data structures using non-blocking techniques. Each paradigm aligns with one of our three objectives for practical and safe memory reclamation algorithms.

Objective 1: Design memory reclamation algorithms that are fast, have a bounded memory footprint, and are easy to use — requiring neither intrusive changes to data structures nor specific architecture or compiler support. These algorithms should also deliver consistent performance across various workloads and be applicable to a wide range of data structures. To achieve this, we introduce the neutralization paradigm with the NBR (Neutralization-Based Reclamation) algorithm and its enhanced version, NBR+ (Optimized Neutralization-Based Reclamation). These algorithms use POSIX signals and a lightweight handshaking mechanism to facilitate safe memory reclamation among threads. By relying solely on atomic reads and writes, they achieve bounded garbage and high performance with minimal overhead compared to existing algorithms. They are straightforward to implement, similar in reasoning and programming effort to two-phased locking, and compatible with numerous data structures.

Objective 2: Eliminate the asymmetric synchronization overhead in existing reclamation algorithms, which often incur costly memory fences while eagerly publishing reservations, as seen in algorithms like hazard pointers and hazard eras. We propose the reactive synchronization paradigm, implemented through deferred memory reclamation and POSIX signals. This mechanism enables threads to privately track memory references (or reservations) and share this information on demand, using the publish-on-ping algorithm. This approach serves as a drop-in replacement for hazard pointers and hazard eras and includes a variant (EpochPOP) that combines epochs with the robustness of hazard pointers to approach the performance of epoch-based reclamation.

Objective 3: Completely eliminate the batching common in current reclamation algorithms to allow immediate memory reclamation, similar to sequential data structures, while maintaining high performance. We introduce Conditional Access, a hardware-software co-design paradigm implemented in a graphite multi-core simulator. This paradigm leverages cache coherence to enable efficient detection of potential use-after-free errors without explicit shared-memory communication or additional coherence traffic. Conditional Access provides programmers with hardware instructions for immediate memory reclamation with minimal overhead in optimistic data structures.

To validate our claims, we designed and conducted extensive benchmark tests to evaluate all proposed algorithms on high-end machines under various scenarios. We paired these algorithms with several real-world concurrent data structures, representing various memory access patterns, and compared their time and space efficiency against numerous state-of-the-art memory reclamation algorithms, demonstrating significant improvements.