Browsing Electrical and Computer Engineering by Subject "timing mismatches"
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Clock Edge Timing Adjustment Techniques for Correction of Timing Mismatches in Interleaved Analog-to-Digital Converters
(University of Waterloo, 2010-09-28)Time-interleaved analog-to-digital converters make use of parallelization to increase the rate at which an analog signal can be digitized. Using M channels at their maximum sampling frequency allows for an overall sampling ...