Now showing items 1-2 of 2

    • A High Performance DDR4 Memory Controller on FPGA 

      Germchi, Danesh (University of Waterloo, 2024-02-22)
      We introduce a high-performance DDR4 SDRAM memory controller synthesizable design for AMD/Xilinx's FPGA devices. Due to limitations in operating frequency, the design on FPGA presents additional challenges compared to ASIC: ...
    • Rank-switching, Open-row DRAM Controller for Mixed-Critical Real-Time Systems 

      Krishnapillai, Yogen (University of Waterloo, 2015-01-16)
      In this thesis, we present a rank-switching open-row DRAM controller for mixed critical real time systems. This memory controller is optimized for multi-requestor and multi-rank memory systems. The key to improved performance ...

      UWSpace

      University of Waterloo Library
      200 University Avenue West
      Waterloo, Ontario, Canada N2L 3G1
      519 888 4883

      All items in UWSpace are protected by copyright, with all rights reserved.

      DSpace software

      Service outages