Silicon Nanowire Based Photodetectors: Modeling and Fabrication
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This research is focused on investigating the role of silicon nanowires in designing high gain, high sensitivity photodetectors, and is based on both device modeling and fabrication. We demonstrate that the superior electrostatic control within the nanowires enables us to effectively engineer the energy band and design novel photodetector architectures. This is due to the high surface to volume ratio in nanowires which allows for the ability to change the electrical properties of a nanowire device in response to a voltage applied to the gate contact. In the first part of the thesis, two photodetector geometries are proposed and theoretically studied. The first geometry is a Metal Oxide Semiconductor (MOS) device with nanowires incorporated in its channel. The next geometry is a junction-less phototransistor, e.g. a photoconductor with a third terminal as the gate. Both geometries are important due to their ability to generate optical gain. For both cases, first the role of nanowire parameters and their pros and cons on the device photo-response is investigated. Afterwards, we propose modifications to the device geometry in order to improve the performance of the device in terms of optical gain and sensitivity. The first modification is allocating a wide region for light absorption in the channel, since single nanowire based photodetectors suffer from lack of efficient absorption, due to their small cross sectional area. Use of phototransistors also helps the photo-current increase, due to the device's internal gain. The second modification incorporates two nanowire/ gate geometries to improve the device photo-response, in terms of both dark- and photo-current. The charge flow in each nanowire is controlled by a gate, which changes the energy band within the nanowire. This band engineering allows for both increasing the optical gain of the phototransistor, and keeping the dark current low. We report nanowire based phototransistors that are potentially able to detect low levels of light intensity (photon rate of less than 50/s). The second part of the thesis is devoted to the fabrication of the nanowire based structures. Top-down approach is used, mainly due to the better control on the nanowire size and position, and repeatability of the processes involved. Fabrication process includes several steps of electron beam lithography, dry and wet etching, metal and dielectric deposition and annealing. Pre-developed recipes are used when available. New recipes are also developed to better suit the specific needs of the devices. The measurement results of the fabricated structures verify most of the concepts proposed in the modeling phase. In the third part of this thesis, we characterize MOS capacitors with and without illumination, based on Silicon on Insulator (SOI) structures used in the previous chapters. Here, we report the first observation of photon induced negative capacitance in a conventional Metal Oxide Semiconductor (MOS) capacitor without the use of ferroelectric materials. Design and implementation of this phenomenon is presented in a capacitor where an aluminum oxide layer serves as the gate dielectric, and the capacitor is in depletion mode. Through extensive modeling, we establish that trap states at the semiconductor-oxide interface, coupled with the injection of photo-generated electrons are responsible for the negative capacitance. We find that varying the trap density and/or light intensity can tune the value of the negative capacitance. We show that in the presence of photons, the experimentally measured quasi-static capacitance in depletion is almost twice the value without photons. Further, the measured capacitance is larger than the values in accumulation and inversion.
Cite this work
Anita Fadavi Roudsari (2014). Silicon Nanowire Based Photodetectors: Modeling and Fabrication. UWSpace. http://hdl.handle.net/10012/8647