FPGA Implementation of a Clockless Stochastic LDPC Decoder
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Date
2014-05-16
Authors
Christopher, Ceroici
Journal Title
Journal ISSN
Volume Title
Publisher
University of Waterloo
Abstract
This thesis presents a clockless stochastic low-density parity-check (LDPC)
decoder implemented on a Field-Programmable Gate Array (FPGA).
Stochastic computing reduces the wiring complexity necessary for
decoding by replacing operations such as multiplication and division with
simple logic gates. Clockless decoding increases the throughput of the
decoder by eliminating the requirement for node signals to be synchronized
after each decoding cycle. With this partial-update algorithm the decoder’s
speed is limited by the average wire delay of the interleaver rather than the
worst-case delay. This type of decoder has been simulated in the past but
not implemented on silicon. The design is implemented on an ALTERA
Stratix IV EP4SGX230 FPGA and the frame error rate (FER) performance,
throughput and power consumption are presented for (96,48) and (204,102)
decoders.
Description
Keywords
Channel coding, LDPC codes, Stochastic signal processing, Digital Circuits