Design and Implementation of a Multi-Channel Field-Programmable Analog Front-End For a Neural Recording System

Abstract

Neural recording systems have attracted an increasing amount of attention in recent years, and researchers have put major efforts into designing and developing devices that can record and monitor neural activity. Understanding the functionality of neurons can be used to develop neuroprosthetics for restoring damages in the nervous system. An analog front-end block is one of the main components in such systems, by which the neuron signals are amplified and processed for further analysis.

In this work, our goal is to design and implement a field-programmable 16-channel analog front-end block, where its programmability is used to deal with process variation in the chip. Each channel consists of a two-stage amplifier as well as a band-pass filter with digitally tunable low corner frequency. The 16 recording channels are designed using four different architectures. The first group of recording channels employs one low-noise amplifier (LNA) as the first-stage amplifier and a fully differential amplifier for the second stage along with an NMOS transistor in the feedback loop. In the second group of architectures, we use an LNA as the first stage and a single-ended amplifier for implementing the second stage. Groups three and four have the same design as groups one and two; however the NMOS transistor in the feedback loop is replaced by two PMOS transistors.

In our design, the circuits are optimized for low noise and low power consumption. Simulations result in input-referred noise of 6.9 μVrms over 0.1 Hz to 1 GHz. Our experiments show the recording channel has a gain of 77.5 dB. The chip is fabricated in AMS 0.35 μm CMOS technology for a total die area of 3 mm×3 mm and consumes 2.7 mW power from a 3.3 V supply. Moreover, the chip is tested on a PCB board that can be employed for in-vivo recording.