dc.contributor.author | Bray, Adam | |
dc.date.accessioned | 2013-12-02 19:58:52 (GMT) | |
dc.date.available | 2013-12-02 19:58:52 (GMT) | |
dc.date.issued | 2013-12-02 | |
dc.date.submitted | 2013-11-22 | |
dc.identifier.uri | http://hdl.handle.net/10012/8053 | |
dc.description.abstract | Time-interleaved analog-to-digital converters are an attractive architecture for achieving a high speed, high resolution ADC in a power efficient manner. However, due to process and manufacturing variations, timing skews occur between the sampling clocks of the sub ADCs within the TI-ADC. These timing skews compromise the spurious free dynamic range of the converter. In addition, jitter on the sampling clocks, degrades the signal-to-noise ratio of the TI-ADC. Therefore, in order to maintain an acceptable spurious free dynamic range and signal to noise ratio, it is necessary to correct the timing skews while adding minimal jitter.
Two analog-based architectures for correcting timing skews were investigated, with one being selected for implementation. The selected architecture and additional test circuitry were designed and fabricated in a 0.18µm CMOS process and tested using a 125 MSPS 16 bit ADC. The circuit achieves a correction precision on the order of 10’s of femtoseconds for timing skews as large as approximately 180 picoseconds, while adding less than 200 femtoseconds of rms jitter. | en |
dc.language.iso | en | en |
dc.publisher | University of Waterloo | en |
dc.subject | ADC | en |
dc.subject | Analog to Digital Converter | en |
dc.subject | Converters | en |
dc.subject | Jitter | en |
dc.subject | Timing Skew | en |
dc.subject | Interleaved | en |
dc.subject | TI-ADC | en |
dc.subject | Time Interleaved | en |
dc.subject | Analog | en |
dc.title | A Low Jitter Analog Circuit for Precisely Correcting Timing Skews in Time Interleaved Analog-to-Digital Converters | en |
dc.type | Master Thesis | en |
dc.pending | false | |
dc.subject.program | Electrical and Computer Engineering | en |
uws-etd.degree.department | Electrical and Computer Engineering | en |
uws-etd.degree | Master of Applied Science | en |
uws.typeOfResource | Text | en |
uws.peerReviewStatus | Unreviewed | en |
uws.scholarLevel | Graduate | en |