Test Chip Design for Process Variation Characterization in 3D Integrated Circuits
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Date
2013-09-23T13:49:25Z
Authors
O'Sullivan, Conor
Journal Title
Journal ISSN
Volume Title
Publisher
University of Waterloo
Abstract
A test chip design is presented for the characterization of process variations and Through
Silicon Via (TSV) induced mechanical stress in 3D integrated circuits. The chip was de-
signed, layed-out, and taped-out for fabrication in a 130nm Tezzaron/GlobalFoundries
process through CMC microsystems. The test chip takes advantage of the architecture
of 3D ICs to split its test structure onto the two tiers of the 3D IC, achieving a device
array density of 40.94 m2 per device. The design also has a high spatial resolution and
measurement delity compared to similar 2D variation characterization test structures.
Background leakage subtraction and radial ltering are two techniques that are ap-
plied to the chip's measurements to reduce its error further for subthreshold device current
measurements and stress-induced mobility measurements, respectively. Experimental mea-
surements are be taken from the chip using a custom PCB measurement setup once the
chip has returned from fabrication.
Description
Keywords
3D, TSV, process variations