High Efficiency Two-Stage GaN Power Amplifier with Improved Linearity
MetadataShow full item record
The trade-off between linearity and efficiency is the key limiting factor to wideband power amplifier design. Current wireless research focuses much of its effort on building power amplifiers with the two aforementioned criteria going hand in hand to build an optimal design. This thesis investigates the sources of nonlinearity associated with GaN high electron mobility transistors (HEMT), and their subsequent effects on the linearity metrics of the power amplifier. The investigation began with an analysis of the sources of nonlinearity, and then a design-based approach to mitigate those sources of nonlinearity was developed. This design approach was compared with existing trends in power amplifier design. The device technology used in the design was CREE GaN HEMT (45W and 6W). In this report, a systematic approach to designing a two stage power amplifier is discussed, and analyzed for design of linear and highly efficient power amplifiers for base stations. The designed power amplifier consists of two stages: a driver stage and a power stage. The driver stage aimed to linearize the power stage by using circuit analysis and transistor properties along with providing the necessary gain. The power stage was built to complement the driver stage and to achieve high efficiency for the power amplifier. An inter-stage matching network placed between the two stages allowed for the required matching of impedances; transmission lines in the bias feed controlled the harmonic impedances for optimal performance without disrupting performance at fundamental frequencies. This approach effectively improved, and maintained, high efficiency over 200MHz of bandwidth. The design approach was simulated and fabricated in order to test the feasibility of linear power amplifier operation with the use of digital pre-distortion (DPD). The fabricated prototype achieved about 70% peak efficiency over the bandwidth and maintained linearity above 40dBc adjacent channel leakage ratio (ACLR) and below 3% error vector magnitude (EVM). The measurement results indicated that the need for DPD was eliminated when the power amplifier was operating in back-off at the center frequency (800MHz). This thesis compares the prototyped design with existing multistage designs which use linear drivers. The report provides conclusions derive from measurement results and bandwidth limitations faced throughout the course of the design. Lastly, potential research directions, which may allow researchers to overcome the limitations of this design, are discussed.