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dc.contributor.authorHung, Austinen 14:02:31 (GMT) 14:02:31 (GMT)
dc.description.abstractRapid progress in the area of Field-Programmable Gate Arrays (FPGAs) has led to the availability of softcore processors that are simple to use, and can enable the development of a fully working system in minutes. This has lead to the enormous popularity of System-On-Programmable-Chip (SOPC) computing platforms. These softcore processors, while relatively simple compared to their leading-edge hardcore counterparts, are often designed with a number of advanced performance-enhancing features, such as instruction and data caches. Moreover, they are designed to be used in a uniprocessor or uncoupled multiprocessor architecture, and not in a tightly-coupled multiprocessing architecture. As a result, traditional cache-coherency protocols are not suitable for use with such systems. This thesis describes a system for enforcing cache coherency on symmetric multiprocessing (SMP) systems using softcore processors. A hybrid protocol that incorporates hardware and software to enforce cache coherency is presented.en
dc.format.extent1009572 bytes
dc.publisherUniversity of Waterlooen
dc.rightsCopyright: 2004, Hung, Austin. All rights reserved.en
dc.subjectElectrical & Computer Engineeringen
dc.subjectcache coherencyen
dc.titleCache Coherency for Symmetric Multiprocessor Systems on Programmable Chipsen
dc.typeMaster Thesisen
dc.pendingfalseen and Computer Engineeringen
uws-etd.degreeMaster of Applied Scienceen

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