UWSpace is currently experiencing technical difficulties resulting from its recent migration to a new version of its software. These technical issues are not affecting the submission and browse features of the site. UWaterloo community members may continue submitting items to UWSpace. We apologize for the inconvenience, and are actively working to resolve these technical issues.
 

Cache Coherency for Symmetric Multiprocessor Systems on Programmable Chips

Thumbnail Image

Files

a2hung2004.pdf (985.91 KB)

Date

2004

Authors

Hung, Austin

Journal Title

Journal ISSN

Volume Title

Publisher

University of Waterloo

Abstract

Rapid progress in the area of Field-Programmable Gate Arrays (FPGAs) has led to the availability of softcore processors that are simple to use, and can enable the development of a fully working system in minutes. This has lead to the enormous popularity of System-On-Programmable-Chip (SOPC) computing platforms. These softcore processors, while relatively simple compared to their leading-edge hardcore counterparts, are often designed with a number of advanced performance-enhancing features, such as instruction and data caches. Moreover, they are designed to be used in a uniprocessor or uncoupled multiprocessor architecture, and not in a tightly-coupled multiprocessing architecture. As a result, traditional cache-coherency protocols are not suitable for use with such systems. This thesis describes a system for enforcing cache coherency on symmetric multiprocessing (SMP) systems using softcore processors. A hybrid protocol that incorporates hardware and software to enforce cache coherency is presented.

Description

Keywords

Electrical & Computer Engineering, FPGA, SOPC, SMP, cache coherency

LC Keywords

Citation

URI

http://hdl.handle.net/10012/764

Collections

Theses
Electrical and Computer Engineering