On-Chip Power Supply Noise: Scaling, Suppression and Detection

Abstract

Design metrics such as area, timing and power are generally considered as the primary criteria in the design of modern day circuits, however, the minimization of power supply noise, among other noise sources, is appreciably more important since not only can it cause a degradation in these parameters but can cause entire chips to fail. Ensuring the integrity of the power supply voltage in the power distribution network of a chip is therefore crucial to both building reliable circuits as well as preventing circuit performance degradation. Power supply noise concerns, predicted over two decades ago, continue to draw significant attention, and with present CMOS technology projected to keep on scaling, it is shown in this work that these issues are not expected to diminish. This research also considers the management and on-chip detection of power supply noise. There are various methods of managing power supply noise, with the use of decoupling capacitors being the most common technique for suppressing the noise. An in-depth analysis of decap structures including scaling effects is presented in this work with corroborating silicon results. The applicability of various decaps for given design constraints is provided. It is shown that MOS-metal hybrid structures can provide a significant increase in capacitance per unit area compared to traditional structures and will continue to be an important structure as technology continues to scale. Noise suppression by means of current shifting within the clock period of an ALU block is further shown to be an additional method of reducing the minimum voltage observed on its associated supply. A simple, and area and power efficient technique for on-chip supply noise detection is also proposed.