Investigation of Current Sensing Using Inherent Resistance

Abstract

A novel method of current sensing using resistance of power delivery path is introduced as a mean to measure static or dynamic load current in high-power system-on-chips, where conventional methods deemed inadequate. It is named “IRS” here, and it stands for Inherent Resistance Current Sensing.

To explain its application and to provide motivation beyond this work, pros and cons of conventional techniques are reviewed with a look at previous works done in this area.

It is followed with review of discreet implementation of the sensor (IRS) in chapter three. The measurements results collected using the discrete circuits are included with an in-depth analysis of the results and compensation techniques. It offers insight to effectiveness of the solution and its potential, while highlighting shortcomings and limitation of discrete implementation. This would set the tone to design integrated version of the sensor.

In order to select amplifier architecture, a rundown of common methods to construct the instrumentation amplifier is discussed in chapter 4, primarily based on the latest work already done in this field per cited references. This is to help readers to get an overall view of the challenges and techniques to overcome them.

Finally, the architecture for the integrated version of the sensor (IRS) is presented, with a proof of concept design. The design is targeted for low voltage VLSI systems to allow integration within large SoCs such as GPUs and CPUs. The primary block, the instrumentation amplifier, is constructed using rail-to-rail current conveyers and simulated using TSMC 32nm process node. The simulation results are analyzed and observations are provided.