Design of CMOS Distributed Amplifiers for Broadband Wireline and Wireless Communication Applications
Khodayari Moez, Kambiz
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While the RF building blocks of narrowband system-on-chip designs have increasingly been created in CMOS during the past decade, researchers have started to look at the possibility of implementation of broadband transceivers in CMOS technology. High speed optical links with operating frequencies of up to 40 GHz and ultra wideband (UWB) wireless systems operating in 3 to 10 GHz frequency band are examples of these broadband applications. CMOS offers a low fabrication cost, and a higher level of integration compared with compound semiconductor technologies that currently claim broadband RFIC applications. <br /><br /> In this work, we focus on the design of broadband low-noise amplifiers: the fundamental building blocks of high data rate wireline and wireless telecommunication systems. A well established microwave engineering technique -distributed amplification- with a potential bandwidth up to the cut-off frequency of transistors is employed. However, the implementation of distributed amplifiers in CMOS imposes new challenges, such as gain attenuation because of substrate loss of on-chip inductors, a typical large die area, and a large noise-figure. These problems have been addressed in this dissertation as described below. <br /><br /> On-chip inductors, the essential components of the distributed amplifiers' gate and drain transmission lines, dissipate more and more power in silicon substrates as well as in metal lines as frequency increases, which in turn reduces the gain and deteriorates the input/output matching. Using active negative resistors implemented by a capacitively source degenerated configuration, we have fully compensated the loss of the transmission lines in order to achieve a flat gain of 10 dB over the entire DC-to-44 GHz bandwidth. <br /><br /> We have addressed another drawback of distributed amplifiers, large die area, by utilizing closely-placed RF transmission lines instead of spiral inductors. Because of a more compact implementation of transmission lines, the area of the distributed amplifiers is considerably reduced at the expense of extra design steps required for the modeling of the closely-placed RF transmission lines. A post-layout simulation method is developed to take into account the effect of inductive and capacitive coupling by incorporating a 3D EM simulator into the design process. A 9-dB 27-GHz distributed amplifier has been fabricated in an area as small as 0. 17 <em>mm</em><sup>2</sup> using 180nm TSMC's CMOS process. <br /><br /> For wireless applications (UWB), a very low-noise figure is required for the broadband preamplifier. Conventional distributed amplifiers fail to provide a low noise figure mainly because of the noise injected by the terminating resistor of the gate transmission lines. We have replaced the terminating resistor with a frequency-dependent resistor which trades off the low frequency input matching of the distributed amplifier (not required for UWB) with a better noise performance. Our proposed design provides a gain of 12 dB with an average noise figure of 3. 4 dB over the entire 3-10 GHz band, advancing the state-of-the-art implementation of broadband LNAs.
Cite this work
Kambiz Khodayari Moez (2006). Design of CMOS Distributed Amplifiers for Broadband Wireline and Wireless Communication Applications. UWSpace. http://hdl.handle.net/10012/2857