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dc.contributor.authorBahlmann, Andrew Richard
dc.date.accessioned2022-12-20 18:55:10 (GMT)
dc.date.issued2022-12-20
dc.date.submitted2022-12-11
dc.identifier.urihttp://hdl.handle.net/10012/18970
dc.description.abstractWith the continued scaling of field-effect transistors (FETs) we have past the point where short-channel effects (SCEs) become a dominate factor in device performance. In particular, FETs suffer from increased leakage currents in their OFF-state, resulting in sub-optimal performance characteristics. Simultaneously, increased power densities place a strain on methods of cooling computer processors. To alleviate these effects and meet future computing demands, there are two avenues of research which must be pursued in parallel, namely, (i) low-power FETs which operate at reduced supply voltages, achieving their ON-state currents at lower gate voltages and (ii) multi-gate FET architectures which aid in the mitigation of SCEs by increasing gate controllability. This thesis addresses these obstacles and possible solutions by studying multi-gate negative capacitance (NC) FETs, whereby a ferroelectric (FE) material is used to modify the gate structure and increase the electric field to improve device performance. Computer simulations in Synopsys Sentaurus TCAD are used to simulate the device operation of NCFETs and study the use of FE material layers in the gate stack of multi-gate FETs. The body of this thesis is composed of two works of original research. The first studies the effect of a tapered NC-FinFET structure on the resulting device performance characteristics. The simulation results of devices with a tapered fin and FE layer indicate the optimum subthreshold swing and ON-state current can be obtained when the taper of the fin is minimal and the taper of the FE is significant. The second work investigates the relationship between statistical variations in the FE thickness of an NC nanosheet (NS) FET device and its resulting performance. The simulated sample sets of NC-NSFET devices show that as the variance of the FE thickness decreases the variability in performance characteristics diminishes. Guidelines are established for obtaining a particular variance in performance metrics which depend on the variance in FE material thickness. The research conducted in these works establishes design principles of multi-gate NCFET devices for specific applications and target performances, expands the contemporary understanding of FE materials for achieving NC enhancement in multi-gate FETs, and will aid engineers and designers in the continued scaling of FET technology without sacrificing future performance criteria.en
dc.language.isoenen
dc.publisherUniversity of Waterlooen
dc.subjectmulti-gate FETen
dc.subjectFinFETen
dc.subjectnanosheet FETen
dc.subjectnegative capacitanceen
dc.subjectferroelectricen
dc.subjectLandau modelen
dc.subjectSentaurus TCADen
dc.titleNumerical and Statistical Performance Analysis of Multi-Gate Negative Capacitance Field-Effect Transistorsen
dc.typeMaster Thesisen
dc.pendingfalse
uws-etd.degree.departmentElectrical and Computer Engineeringen
uws-etd.degree.disciplineElectrical and Computer Engineering (Nanotechnology)en
uws-etd.degree.grantorUniversity of Waterlooen
uws-etd.degreeMaster of Applied Scienceen
uws-etd.embargo.terms2 yearsen
uws.contributor.advisorYoon, Youngki
uws.contributor.affiliation1Faculty of Engineeringen
uws.published.cityWaterlooen
uws.published.countryCanadaen
uws.published.provinceOntarioen
uws-etd.embargo2024-12-19T18:55:10Z
uws.typeOfResourceTexten
uws.peerReviewStatusUnrevieweden
uws.scholarLevelGraduateen


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