dc.contributor.author | Yan, Yangtian | |
dc.date.accessioned | 2022-08-26 14:15:55 (GMT) | |
dc.date.available | 2022-08-26 14:15:55 (GMT) | |
dc.date.issued | 2022-08-26 | |
dc.date.submitted | 2022-08-19 | |
dc.identifier.uri | http://hdl.handle.net/10012/18648 | |
dc.description.abstract | Spiking neural networks (SNNs) are an emerging class of biologically inspired Artificial Neural
Networks implemented in machine learning and artificial intelligence. Current state-of-the-art
small- and large-scale SNNs are mainly implemented as digital hardware with time-multiplexing
techniques to achieve power efficiency. In this thesis, a 65 nm CMOS mixed signal
asynchronous SNN implementation was designed and simulated. The proposed design reduces
hardware and timing complexity over existing implementations and opens opportunities for
further larger-scale implementations. | en |
dc.language.iso | en | en |
dc.publisher | University of Waterloo | en |
dc.relation.uri | MNIST | en |
dc.subject | artificial intelligence | en |
dc.subject | CMOS | en |
dc.subject | neural network | en |
dc.subject | artificial neural network | en |
dc.subject | spiking neural network | en |
dc.subject | machine learning | en |
dc.subject | mixed signal IC | en |
dc.title | A Mixed Signal 65nm CMOS Implementation of a Spiking Neural Network | en |
dc.type | Master Thesis | en |
dc.pending | false | |
uws-etd.degree.department | Electrical and Computer Engineering | en |
uws-etd.degree.discipline | Electrical and Computer Engineering | en |
uws-etd.degree.grantor | University of Waterloo | en |
uws-etd.degree | Master of Applied Science | en |
uws-etd.embargo.terms | 0 | en |
uws.contributor.advisor | Wright, Derek | |
uws.contributor.affiliation1 | Faculty of Engineering | en |
uws.published.city | Waterloo | en |
uws.published.country | Canada | en |
uws.published.province | Ontario | en |
uws.typeOfResource | Text | en |
uws.peerReviewStatus | Unreviewed | en |
uws.scholarLevel | Graduate | en |