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dc.contributor.authorHeld, Stephan
dc.contributor.authorSpirkl, Sophie 00:31:52 (GMT) 00:31:52 (GMT)
dc.description© Stephan Held and Sophie Spirkl | ACM 2018. This is the author's version of the work. It is posted here for your personal use. Not for redistribution. The definitive Version of Record was published in Algorithms,
dc.description.abstractWe consider the problem of constructing fast and small binary adder circuits. Among widely used adders, the Kogge-Stone adder is often considered the fastest, because it computes the carry bits for two n-bit numbers (where n is a power of two) with a depth of 2 log2n logic gates, size 4 nlog2n, and all fan-outs bounded by two. Fan-outs of more than two are disadvantageous in practice, because they lead to the insertion of repeaters for repowering the signal and additional depth in the physical implementation. However, the depth bound of the Kogge-Stone adder is off by a factor of two from the lower bound of log2n. Two separate constructions by Brent and Krapchenko achieve this lower bound asymptotically. Brent’s construction gives neither a bound on the fan-out nor the size, while Krapchenko’s adder has linear size, but can have up to linear fan-out. With a fan-out bound of two, neither construction achieves a depth of less than 2 log2n. In a further approach, Brent and Kung proposed an adder with linear size and fan-out two but twice the depth of the Kogge-Stone adder. These results are 33–43 years old and no substantial theoretical improvement for has been made since then. In this article, we integrate the individual advantages of all previous adder circuits into a new family of full adders, the first to improve on the depth bound of 2 log2n while maintaining a fan-out bound of two. Our adders achieve an asymptotically optimum logic gate depth of log2n + o(log 2n) and linear size O(n).en
dc.publisherAssociation for Computing Machineryen
dc.rightsAttribution-NonCommercial 4.0 International*
dc.subjectbinary additionen
dc.subjectcombinational complexityen
dc.titleBinary Adder Circuits of Asymptotically Minimum Depth, Linear Size, and Fan-Out Twoen
dcterms.bibliographicCitationHeld, S., & Spirkl, S. T. (2017). Binary Adder Circuits of Asymptotically Minimum Depth, Linear Size, and Fan-Out Two. ACM Transactions on Algorithms, 14(1), 4:1-4:18.
uws.contributor.affiliation1Faculty of Mathematicsen
uws.contributor.affiliation2Combinatorics and Optimizationen

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