dc.contributor.author Wasly, Saud dc.contributor.author Pellizzoni, Rodolfo dc.contributor.author Kapre, Nachiket dc.date.accessioned 2017-10-30 19:10:39 (GMT) dc.date.available 2017-10-30 19:10:39 (GMT) dc.date.issued 2017-10-30 dc.identifier.uri http://hdl.handle.net/10012/12600 dc.description.abstract Overlay NoCs, such as Hoplite, are cheap to implement on an FPGA but provide no bounds on worst-case routing latency of packets traversing the NoC due to deflection routing. In this paper, we show how to adapt Hoplite to enable calculation of precise upper bounds on routing latency by modifying the routing function to prioritize deflections, and by regulating the injection of packets to meet certain throughput and burstiness constraints. We provide an en analytical model for computing end-to-end latency in the form of (1) in-flight time in the network $T^f$, and (2) waiting time at the source node $T^s$. To bound in-flight time in an $m \times m$ NoC, we modify the routing function and switching crossbar richness in the Hoplite router to deliver $T^{f} =\Delta X + \Delta Y + (\Delta Y \times m) + 2$ where $\Delta X$ and $\Delta Y$ are differences of the source and destination address co-ordinates of the packet. To bound the waiting time at the source, we add a Token Bucket regulator with rate $\rho_i$ and burstiness $\sigma_i$ for each flow $f_i$node $(x,y)$ to deliver $(\lceil\frac{1}{\rho_{_i}}\rceil -1 ) + T^s$ : $T^s =\lceil\frac{\sigma(\Gamma^C_f){1-\rho(\Gamma^C_f)} \rceil$ which depends on the regulator period $1/\rho_i$, burstiness $\sigma$ and the rate $\rho$ of all interfering flows $\Gamma^C_f$. A 64b implementation of our HopliteRT routerrequires $\approx$4\% fewer LUTs, and similar number of FFs compared to the original Hoplite router. We also need two small counters at each client port for regulating injection. We evaluate our model and RTL implementation across synthetic traffic patterns and observe behavior that conforms with the analytical bounds. dc.language.iso en en dc.subject NoC en dc.subject Real-time en dc.subject FPGA en dc.subject Latency Analysis en dc.title Worst Case Latency Analysis for Hoplite FPGA-based NoC en dc.type Technical Report en dcterms.bibliographicCitation S. Wasly, R. Pellizzoni, and N. Kapre, “Analysis of Worst Case Latency for Hoplite FPGA-based NoC,” University of Waterloo, Technical, Oct. 2017. en uws.contributor.affiliation1 Faculty of Engineering en uws.contributor.affiliation2 Electrical and Computer Engineering en uws.typeOfResource Text en uws.peerReviewStatus Unreviewed en uws.scholarLevel Faculty en
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