Design Strategy of 2D Material Field-Effect Transistors: Engineering the Number of Layers in Phosphorene FETs

Abstract

Thickness or the number of layers in 2D semiconductors is a key parameter to determine the material’s electronic properties and the overall device performance of 2D material electronics. Here we discuss the engineering practice of optimizing material and device parameters of phosphorene field-effect transistors (FETs) by means of self-consistent atomistic quantum transport simulations, where the impacts of different numbers of phosphorene layers on various device characteristics are explored in particular, considering two specific target applications of high-performance and low-power devices. Our results suggest that, for high-performance applications, monolayer phosphorene should be utilized in conventional FET structure since it can provide the equally large on current as other multilayer phosphorenes (I_on > 1 mA/μm) without showing a penalty of relatively lower density of states, along with favorableness for steep switching and large immunity to gate-induced drain leakage. On the other hand, more comprehensive approach is required for low-power applications, where operating voltage, doping concentration, and channel length should be carefully engineered along with the thickness of phosphorene in tunnel FET (TFET) structure to achieve ultra-low leakage current without sacrificing on current significantly. Our extensive simulation results revealed that either bilayer or trilayer phosphorene can provide the best performance in TFET with the maximum I_on/I_off of ~2x10¹¹ and the subthreshold swing as low as 13 mV/dec. In addition, our comparative study of phosphorene-based conventional FET and TFET clearly shows the feasibility and the limitation of each device for different target applications, providing irreplaceable insights into the design strategy of phosphorene FETs that can be also extended to other similar layered material electronic devices.