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dc.contributor.authorTao, Jianian 16:37:22 (GMT) 16:37:22 (GMT)
dc.description.abstractThis thesis investigates the phase noise of two different 2-stage cross-coupled pair unsaturated ring oscillators with no tail current source. One oscillator consists of top cross-coupled pair delay cells, and the other consists of top cross-coupled pair and bottom cross-coupled pair delay cells. Under a low supply voltage restriction, a phase noise model is developed and applied to both ring oscillators. Both top cross-coupled pair and top and bottom cross-coupled pair oscillators are fabricated with 0.13 um CMOS technology. Phase noise measurements of -92 dBc/Hz and -89 dBc/Hz ,respectively, at 1 MHz offset is obtained from the chip, which agree with theory and simulations. Top cross-coupled ring oscillator, with phase noise of -92 dBc/Hz at 1 MHz offset, is implemented in a second order sigma-delta time to digital converter. System level and transistor level functional simulation and timing jitter simulation are obtained.en
dc.publisherUniversity of Waterlooen
dc.subjectPhase noiseen
dc.subjecttime to digital converteren
dc.subjectsigma delta modulatoren
dc.titleDesign of Low Voltage Unsaturated Ring Oscillator for a Sigma Delta Time to Digital Converteren
dc.typeMaster Thesisen
dc.pendingfalse and Computer Engineeringen and Computer Engineeringen of Waterlooen
uws-etd.degreeMaster of Applied Scienceen
uws.contributor.advisorLeung, Bosco
uws.contributor.affiliation1Faculty of Engineeringen

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