dc.contributor.author | Guo, Danlu | |
dc.date.accessioned | 2016-12-23 17:35:14 (GMT) | |
dc.date.available | 2016-12-23 17:35:14 (GMT) | |
dc.date.issued | 2016-12-23 | |
dc.date.submitted | 2016-12-22 | |
dc.identifier.uri | http://hdl.handle.net/10012/11138 | |
dc.description.abstract | The DRAM main memory is a critical component and a performance bottleneck of almost all computing systems. Since the DRAM is a shared memory resource on multi-core plat- forms, all cores contend for the memory bandwidth. Therefore, there is a keen interest in the real-time community to design predictable DRAM controllers to provide a low memory access latency bound to meet the strict timing requirement of real-time applications.
Due to the lack of generalization of publicly available DRAM controller models in full-system and DRAM device simulators, researchers often design in-house simulator to validate their designs. An extensible cycle-accurate DRAM controller simulation frame- work is developed to simplify the process of validating new DRAM controller designs. To prove the extensibility and reusability of the framework, ten state-of-the-art predictable DRAM controllers are implemented in the framework with less than 200 lines of new code.
With the help of the framework, a comprehensive evaluation of state-of-the-art pre- dictable DRAM controllers is performed analytically and experimentally to show the im- pact of different system parameters. This extensive evaluation allows researchers to assess the contribution of state-of-the-art DRAM controller approaches.
At last, a novel DRAM controller with request reordering technique is proposed to provide a configurable trade-off between latency bound and bandwidth in mixed-critical systems. Compared to the state-of-the-art DRAM controller, there is a balance point between the two designs which depends on the locality of the task under analysis and the DRAM device used in the system. | en |
dc.language.iso | en | en |
dc.publisher | University of Waterloo | en |
dc.subject | Real-Time System | en |
dc.subject | DRAM Controller | en |
dc.title | A Comprehensive Study of DRAM Controllers in Real-Time Systems | en |
dc.type | Master Thesis | en |
dc.pending | false | |
uws-etd.degree.department | Electrical and Computer Engineering | en |
uws-etd.degree.discipline | Electrical and Computer Engineering | en |
uws-etd.degree.grantor | University of Waterloo | en |
uws-etd.degree | Master of Applied Science | en |
uws.contributor.advisor | Pellizzoni, Rodolfo | |
uws.contributor.affiliation1 | Faculty of Engineering | en |
uws.published.city | Waterloo | en |
uws.published.country | Canada | en |
uws.published.province | Ontario | en |
uws.typeOfResource | Text | en |
uws.peerReviewStatus | Unreviewed | en |
uws.scholarLevel | Graduate | en |